diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/media/video/Kconfig linux-2.6.8.1/drivers/media/video/Kconfig --- linux-2.6.8.1.org/drivers/media/video/Kconfig 2004-08-14 19:56:22.000000000 +0900 +++ linux-2.6.8.1/drivers/media/video/Kconfig 2004-08-30 10:24:01.000000000 +0900 @@ -306,5 +306,12 @@ To compile this driver as a module, choose M here: the module will be called ovcamchip +config M32R_AR + tristate "AR devices" + +config M32R_AR_VGA + tristate "Use Colour AR module (VGA)" + depends on M32R_AR + endmenu diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/media/video/Makefile linux-2.6.8.1/drivers/media/video/Makefile --- linux-2.6.8.1.org/drivers/media/video/Makefile 2004-08-14 19:55:10.000000000 +0900 +++ linux-2.6.8.1/drivers/media/video/Makefile 2004-08-30 10:24:01.000000000 +0900 @@ -47,3 +47,5 @@ obj-$(CONFIG_VIDEO_TUNER) += tuner.o tda9887.o obj-$(CONFIG_VIDEO_BUF) += video-buf.o obj-$(CONFIG_VIDEO_BTCX) += btcx-risc.o + +obj-$(CONFIG_M32R_AR_VGA) += arv.o diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/media/video/arv.c linux-2.6.8.1/drivers/media/video/arv.c --- linux-2.6.8.1.org/drivers/media/video/arv.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/media/video/arv.c 2004-07-29 10:58:28.000000000 +0900 @@ -0,0 +1,883 @@ +/* + * Colour AR M64278(VGA) driver for Video4Linux + * + * Copyright (C) 2003 Takeo Takahashi + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Some code is taken from AR driver sample program for M3T-M32700UT. + * + * AR driver sample (M32R SDK): + * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION + * AND RENESAS SOLUTIONS CORPORATION + * All Rights Reserved. + * + * 2003-09-01: Support w3cam by Takeo Takahashi + * + * $Id: arv.c,v 1.2 2004/07/29 01:58:28 fujiwara Exp $ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arv.h" + +#if 0 +#define DEBUG(n, args...) printk(args) +#define CHECK_LOST 1 +#else +#define DEBUG(n, args...) +#define CHECK_LOST 0 +#endif + +/* + * USE_INT is always 0, interrupt mode is not available + * on linux due to lack of speed + */ +#define USE_INT 0 /* Don't modify */ + +#define VERSION "0.02" + +#define ar_inl(addr) inl((unsigned long)(addr)) +#define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr)) + +extern struct cpuinfo_m32r boot_cpu_data; + +/* + * CCD pixel size + * Note that M32700UT does not support CIF mode, but QVGA is + * supported by M32700UT hardware using VGA mode of AR LSI. + * + * Supported: VGA (Normal mode, Interlace mode) + * QVGA (Always Interlace mode of VGA) + * + */ +#define AR_WIDTH_VGA 640 +#define AR_HEIGHT_VGA 480 +#define AR_WIDTH_QVGA 320 +#define AR_HEIGHT_QVGA 240 +#define MIN_AR_WIDTH AR_WIDTH_QVGA +#define MIN_AR_HEIGHT AR_HEIGHT_QVGA +#define MAX_AR_WIDTH AR_WIDTH_VGA +#define MAX_AR_HEIGHT AR_HEIGHT_VGA + +/* bits & bytes per pixel */ +#define AR_BITS_PER_PIXEL 16 +#define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8) + +/* line buffer size */ +#define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL) +#define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL) +#define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA + +/* frame size & type */ +#define AR_FRAME_BYTES_VGA (AR_WIDTH_VGA * AR_HEIGHT_VGA * \ + AR_BYTES_PER_PIXEL) +#define AR_FRAME_BYTES_QVGA (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * \ + AR_BYTES_PER_PIXEL) +#define MAX_AR_FRAME_BYTES (MAX_AR_WIDTH * MAX_AR_HEIGHT * \ + AR_BYTES_PER_PIXEL) + +#define AR_MAX_FRAME 15 + +/* capture size */ +#define AR_SIZE_VGA 0 +#define AR_SIZE_QVGA 1 + +/* capture mode */ +#define AR_MODE_INTERLACE 0 +#define AR_MODE_NORMAL 1 + +struct ar_device { + struct video_device *vdev; + unsigned int start_capture; // duaring capture in INT. mode. +#if USE_INT + unsigned char *line_buff; // DMA line buffer +#endif + unsigned char *frame[MAX_AR_HEIGHT]; // frame data + short size; // capture size + short mode; // capture mode + int width, height; + int frame_bytes, line_bytes; + wait_queue_head_t wait; + struct semaphore lock; +}; + +static int video_nr = -1; /* video device number (first free) */ +static unsigned char yuv[MAX_AR_FRAME_BYTES]; + +/* module parameters */ +/* default frequency */ +#define DEFAULT_FREQ 50 // 50 or 75 (MHz) is available as BCLK +static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */ +static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */ +static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */ +MODULE_PARM(freq, "i"); +MODULE_PARM(vga, "i"); +MODULE_PARM(vga_interlace, "i"); + +static int ar_initialize(struct video_device *dev); + +/******************************************************************* + * I2C functions + *******************************************************************/ +void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2, unsigned long data3) +{ + int i; + + /* Slave Address */ + ar_outl(addr, PLDI2CDATA); + + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + /* Start */ + ar_outl(1, PLDI2CCND); + + for(i=0; i<1000; i++); + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + + /* Trasfer data 1 */ + ar_outl(data1, PLDI2CDATA); + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); + + /* Ack wait */ + for(i=0; i<1000; i++); + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + + /* Trasfer data 2 */ + ar_outl(data2, PLDI2CDATA); + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); + + /* Ack wait */ + for(i=0; i<1000; i++); + + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + + if(n==3){ + /* Trasfer data 3 */ + ar_outl(data3, PLDI2CDATA); + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); + + /* Ack wait */ + for(i=0; i<10000; i++); + + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + } + + /* Stop */ + for(i=0; i<100; i++); + ar_outl(2, PLDI2CCND); + ar_outl(2, PLDI2CCND); + + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_BB ); +} + + +void init_iic(void) +{ + DEBUG(1, "init_iic:\n"); + + /* + * ICU Setting (iic) + */ + /* I2C Setting */ + ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */ + ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */ + ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */ + + /* I2C CLK */ + /* 50MH-100k */ + if (freq == 75) { + ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */ + } else if (freq == 50) { + ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */ + } else { + ar_outl(244, PLDI2CFREQ); /* default:BCLK = 50MHz */ + } + ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */ +} + +/************************************************************************** + * + * Video4Linux Interface functions + * + **************************************************************************/ +static __inline__ void wait_for_vertical_sync(int exp_line) +{ +#if CHECK_LOST + int tmout = 10000; /* FIXME */ + int l; + + /* + * check HCOUNT because we can not check vertual sync. + */ + for (; tmout >= 0; tmout--) { + l = ar_inl(ARVHCOUNT); + if (l == exp_line) break; + } + if (tmout < 0) + printk("arv: lost %d -> %d\n", exp_line, l); +#else + while (ar_inl(ARVHCOUNT) != exp_line) ; +#endif +} + +static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos) +{ + struct video_device *v = video_devdata(file); + struct ar_device *ar = v->priv; + long ret = ar->frame_bytes; /* return read bytes */ + unsigned long arvcr1 = 0; + unsigned long flags; + unsigned char *p; + int h, w; + unsigned char *py, *pu, *pv; +#if ! USE_INT + int l; +#endif + + DEBUG(1, "ar_read()\n"); + + if (ar->size == AR_SIZE_QVGA) arvcr1 |= ARVCR1_QVGA; + if (ar->mode == AR_MODE_NORMAL) arvcr1 |= ARVCR1_NORMAL; + + down(&ar->lock); + +#if USE_INT + local_irq_save(flags); + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0xa1871300, M32700_DMA0CR0); + ar_outl(0x01000000, M32700_DMA0CR1); + + // set AR FIFO address as source(BSEL5) + ar_outl(ARDATA32, M32700_DMA0CSA); // + ar_outl(ARDATA32, M32700_DMA0RSA); // + ar_outl(ar->line_buff, M32700_DMA0CDA); // destination address + ar_outl(ar->line_buff, M32700_DMA0RDA); // reload address + ar_outl(ar->line_bytes, M32700_DMA0CBCUT); // byte count(bytes) + ar_outl(ar->line_bytes, M32700_DMA0RBCUT); // reload count (bytes) + + /* + * Okey , kicks AR LSI to invoke an interrupt + */ + ar->start_capture = 0; + ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); + local_irq_restore(flags); + /* .... AR interrupts .... */ + interruptible_sleep_on(&ar->wait); + if (signal_pending(current)) { + printk("arv: interrupted while get frame data.\n"); + ret = -EINTR; + goto out_up; + } +#else /* ! USE_INT */ + /* polling */ + ar_outl(arvcr1, ARVCR1); + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0x8000, M32700_DMAEDET); + ar_outl(0xa0861300, M32700_DMA0CR0); + ar_outl(0x01000000, M32700_DMA0CR1); + ar_outl(ARDATA32, M32700_DMA0CSA); + ar_outl(ARDATA32, M32700_DMA0RSA); + ar_outl(ar->line_bytes, M32700_DMA0CBCUT); + ar_outl(ar->line_bytes, M32700_DMA0RBCUT); + + local_irq_save(flags); + while (ar_inl(ARVHCOUNT) != 0) ; // wait for 0 + if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { + for (h = 0; h < ar->height; h++) { + wait_for_vertical_sync(h); + if (h < (AR_HEIGHT_VGA/2)) + l = h << 1; + else + l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1); + ar_outl(virt_to_phys(ar->frame[l]), M32700_DMA0CDA); + ar_outl(0x8080, M32700_DMAEN); // enable DMA0 + while (!(ar_inl(M32700_DMAEDET) & 0x8000)) ; + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0x8000, M32700_DMAEDET);// clear status + ar_outl(0xa0861300, M32700_DMA0CR0); + } + } else { + for (h = 0; h < ar->height; h++) { + wait_for_vertical_sync(h); + ar_outl(virt_to_phys(ar->frame[h]), M32700_DMA0CDA); + ar_outl(0x8080, M32700_DMAEN); // enable DMA0 + while (!(ar_inl(M32700_DMAEDET) & 0x8000)) ; + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0x8000, M32700_DMAEDET);// clear status + ar_outl(0xa0861300, M32700_DMA0CR0); + } + } + local_irq_restore(flags); +#endif /* ! USE_INT */ + + /* + * convert YUV422 to YUV422P + * +--------------------+ + * | Y0,Y1,... | + * | ..............Yn | + * +--------------------+ + * | U0,U1,........Un | + * +--------------------+ + * | V0,V1,........Vn | + * +--------------------+ + */ + py = yuv; + pu = py + (ar->frame_bytes / 2); + pv = pu + (ar->frame_bytes / 4); + for (h = 0; h < ar->height; h++) { + p = ar->frame[h]; + for (w = 0; w < ar->line_bytes; w += 4) { + *py++ = *p++; + *pu++ = *p++; + *py++ = *p++; + *pv++ = *p++; + } + } + if (copy_to_user(buf, yuv, ar->frame_bytes)) { + printk("arv: failed while copy_to_user yuv.\n"); + ret = -EFAULT; + goto out_up; + } + DEBUG(1, "ret = %d\n", ret); +out_up: + up(&ar->lock); + return ret; +} + +static int ar_do_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, void *arg) +{ + struct video_device *dev = video_devdata(file); + struct ar_device *ar = dev->priv; + + DEBUG(1, "ar_ioctl()\n"); + switch(cmd) { + case VIDIOCGCAP: + { + struct video_capability *b = arg; + DEBUG(1, "VIDIOCGCAP:\n"); + strcpy(b->name, ar->vdev->name); + b->type = VID_TYPE_CAPTURE; + b->channels = 0; + b->audios = 0; + b->maxwidth = MAX_AR_WIDTH; + b->maxheight = MAX_AR_HEIGHT; + b->minwidth = MIN_AR_WIDTH; + b->minheight = MIN_AR_HEIGHT; + return 0; + } + case VIDIOCGCHAN: + DEBUG(1, "VIDIOCGCHAN:\n"); + return 0; + case VIDIOCSCHAN: + DEBUG(1, "VIDIOCSCHAN:\n"); + return 0; + case VIDIOCGTUNER: + DEBUG(1, "VIDIOCGTUNER:\n"); + return 0; + case VIDIOCSTUNER: + DEBUG(1, "VIDIOCSTUNER:\n"); + return 0; + case VIDIOCGPICT: + DEBUG(1, "VIDIOCGPICT:\n"); + return 0; + case VIDIOCSPICT: + DEBUG(1, "VIDIOCSPICT:\n"); + return 0; + case VIDIOCCAPTURE: + DEBUG(1, "VIDIOCCAPTURE:\n"); + return -EINVAL; + case VIDIOCGWIN: + { + struct video_window *w = arg; + DEBUG(1, "VIDIOCGWIN:\n"); + memset(w, 0, sizeof(w)); + w->width = ar->width; + w->height = ar->height; + return 0; + } + case VIDIOCSWIN: + { + struct video_window *w = arg; + DEBUG(1, "VIDIOCSWIN:\n"); + if(w->width != AR_WIDTH_QVGA && w->height != AR_HEIGHT_QVGA) + if(w->width != AR_WIDTH_VGA && w->height != AR_HEIGHT_VGA) + return -EINVAL; + + down(&ar->lock); + ar->width = w->width; + ar->height = w->height; + if (ar->width == AR_WIDTH_VGA) { + ar->size = AR_SIZE_VGA; + ar->frame_bytes = AR_FRAME_BYTES_VGA; + ar->line_bytes = AR_LINE_BYTES_VGA; + if (vga_interlace) + ar->mode = AR_MODE_INTERLACE; + else + ar->mode = AR_MODE_NORMAL; + } else { + ar->size = AR_SIZE_QVGA; + ar->frame_bytes = AR_FRAME_BYTES_QVGA; + ar->line_bytes = AR_LINE_BYTES_QVGA; + ar->mode = AR_MODE_INTERLACE; + } + up(&ar->lock); + return 0; + } + case VIDIOCGFBUF: + DEBUG(1, "VIDIOCGFBUF:\n"); + return -EINVAL; + case VIDIOCSFBUF: + DEBUG(1, "VIDIOCSFBUF:\n"); + return -EINVAL; + case VIDIOCKEY: + DEBUG(1, "VIDIOCKEY:\n"); + return 0; + case VIDIOCGFREQ: + DEBUG(1, "VIDIOCGFREQ:\n"); + return -EINVAL; + case VIDIOCSFREQ: + DEBUG(1, "VIDIOCSFREQ:\n"); + return -EINVAL; + case VIDIOCGAUDIO: + DEBUG(1, "VIDIOCGAUDIO:\n"); + return -EINVAL; + case VIDIOCSAUDIO: + DEBUG(1, "VIDIOCSAUDIO:\n"); + return -EINVAL; + case VIDIOCSYNC: + DEBUG(1, "VIDIOCSYNC:\n"); + return -EINVAL; + case VIDIOCMCAPTURE: + DEBUG(1, "VIDIOCMCAPTURE:\n"); + return -EINVAL; + case VIDIOCGMBUF: + DEBUG(1, "VIDIOCGMBUF:\n"); + return -EINVAL; + case VIDIOCGUNIT: + DEBUG(1, "VIDIOCGUNIT:\n"); + return -EINVAL; + case VIDIOCGCAPTURE: + DEBUG(1, "VIDIOCGCAPTURE:\n"); + return -EINVAL; + case VIDIOCSCAPTURE: + DEBUG(1, "VIDIOCSCAPTURE:\n"); + return -EINVAL; + case VIDIOCSPLAYMODE: + DEBUG(1, "VIDIOCSPLAYMODE:\n"); + return -EINVAL; + case VIDIOCSWRITEMODE: + DEBUG(1, "VIDIOCSWRITEMODE:\n"); + return -EINVAL; + case VIDIOCGPLAYINFO: + DEBUG(1, "VIDIOCGPLAYINFO:\n"); + return -EINVAL; + case VIDIOCSMICROCODE: + DEBUG(1, "VIDIOCSMICROCODE:\n"); + return -EINVAL; + case VIDIOCGVBIFMT: + DEBUG(1, "VIDIOCGVBIFMT:\n"); + return -EINVAL; + case VIDIOCSVBIFMT: + DEBUG(1, "VIDIOCSVBIFMT:\n"); + return -EINVAL; + default: + DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd); + return -ENOIOCTLCMD; + } + return 0; +} + +static int ar_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, ar_do_ioctl); +} + +#if USE_INT +/* + * Interrupt handler + */ +static void ar_interrupt(int irq, void *dev, struct pt_regs *regs) +{ + struct ar_device *ar = dev; + unsigned int line_count; + unsigned int line_number; + unsigned int arvcr1; + + line_count = ar_inl(ARVHCOUNT); // line number + if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { + /* operations for interlace mode */ + if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */ + line_number = (line_count << 1); + else /* odd line */ + line_number = + (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1); + } else { + line_number = line_count; + } + + if (line_number == 0) { + /* + * It is an interrupt for line 0. + * we have to start capture. + */ + ar_outl(0x8000, M32700_DMAEN); // disable DMA0 + //ar_outl(ar->line_buff, M32700_DMA0CDA); // needless? + memcpy(ar->frame[0], ar->line_buff, ar->line_bytes); + //ar_outl(0xa1861300, M32700_DMA0CR0); + ar_outl(0x8080, M32700_DMAEN); // enable DMA0 + ar->start_capture = 1; // during capture + return; + } + + if (ar->start_capture == 1 && line_number <= (ar->height - 1)) { + ar_outl(0x8000, M32700_DMAEN); // disable DMA0 + memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes); + + /* + * if captured all line of a frame, disable AR interrupt + * and wake a process up. + */ + if (line_number == (ar->height - 1)) { /* end of line */ + + ar->start_capture = 0; + + /* disable AR interrupt request */ + arvcr1 = ar_inl(ARVCR1); + arvcr1 &= ~ARVCR1_HIEN; // clear int. flag + ar_outl(arvcr1, ARVCR1); // disable + wake_up_interruptible(&ar->wait); + } else { + //ar_outl(ar->line_buff, M32700_DMA0CDA); + //ar_outl(0xa1861300, M32700_DMA0CR0); + ar_outl(0x8080, M32700_DMAEN); // enable DMA + } + } +} +#endif + +/* + * ar_initialize() + * ar_initialize() is called by video_register_device() and + * initializes AR LSI and peripherals. + * + * -1 is returned in all failures. + * 0 is returned in success. + * + */ +static int ar_initialize(struct video_device *dev) +{ + struct ar_device *ar = (struct ar_device *)dev->priv; + unsigned long cr = 0; + int i,found=0; + + DEBUG(1, "ar_initialize:\n"); + + /* + * initialize AR LSI + */ + ar_outl(0, ARVCR0); // assert reset of AR LSI + for( i=0; i<0x18; i++); // wait for over 10 cycles @ 27MHz + ar_outl(ARVCR0_RST, ARVCR0); // negate reset of AR LSI (enable) + for( i=0; i<0x40d; i++); // wait for over 420 cycles @ 27MHz + + /* AR uses INT3 of CPU as interrupt pin. */ + ar_outl(ARINTSEL_INT3, ARINTSEL); + + if (ar->size == AR_SIZE_QVGA) cr |= ARVCR1_QVGA; + if (ar->mode == AR_MODE_NORMAL) cr |= ARVCR1_NORMAL; + ar_outl(cr, ARVCR1); + + /* + * Initialize IIC so that CPU can communicate with AR LSI, + * and send boot commands to AR LSI. + */ + init_iic(); + + for( i=0; i<0x100000; i++) // > 0xa1d10, 56ms + if((ar_inl(ARVCR0) & ARVCR0_VDS)){ // VSYNC + found = 1; + break; + } + + if(found == 0) + return -ENODEV; + + printk("arv: Initializing "); + + iic(2,0x78,0x11,0x01,0x00); // start + iic(3,0x78,0x12,0x00,0x06); + iic(3,0x78,0x12,0x12,0x30); + iic(3,0x78,0x12,0x15,0x58); + iic(3,0x78,0x12,0x17,0x30); + printk("."); + iic(3,0x78,0x12,0x1a,0x97); + iic(3,0x78,0x12,0x1b,0xff); + iic(3,0x78,0x12,0x1c,0xff); + iic(3,0x78,0x12,0x26,0x10); + iic(3,0x78,0x12,0x27,0x00); + printk("."); + iic(2,0x78,0x34,0x02,0x00); + iic(2,0x78,0x7a,0x10,0x00); + iic(2,0x78,0x80,0x39,0x00); + iic(2,0x78,0x81,0xe6,0x00); + iic(2,0x78,0x8d,0x00,0x00); + printk("."); + iic(2,0x78,0x8e,0x0c,0x00); + iic(2,0x78,0x8f,0x00,0x00); +// iic(2,0x78,0x90,0x00,0x00); // AWB on=1 off=0 + iic(2,0x78,0x93,0x01,0x00); + iic(2,0x78,0x94,0xcd,0x00); + iic(2,0x78,0x95,0x00,0x00); + printk("."); + iic(2,0x78,0x96,0xa0,0x00); + iic(2,0x78,0x97,0x00,0x00); + iic(2,0x78,0x98,0x60,0x00); + iic(2,0x78,0x99,0x01,0x00); + iic(2,0x78,0x9a,0x19,0x00); + printk("."); + iic(2,0x78,0x9b,0x02,0x00); + iic(2,0x78,0x9c,0xe8,0x00); + iic(2,0x78,0x9d,0x02,0x00); + iic(2,0x78,0x9e,0x2e,0x00); + iic(2,0x78,0xb8,0x78,0x00); + iic(2,0x78,0xba,0x05,0x00); +// iic(2,0x78,0x83,0x8c,0x00); // brightness + printk("."); + + // color correction +#if 0 + iic(3,0x78,0x49,0x00,0x89); // a + iic(3,0x78,0x49,0x01,0x96); // b + iic(3,0x78,0x49,0x03,0x85); // c + iic(3,0x78,0x49,0x04,0x87); // d + iic(3,0x78,0x49,0x02,0x66); // e(Lo) + iic(3,0x78,0x49,0x05,0x84); // f(Lo) + iic(3,0x78,0x49,0x06,0x04); // e(Hi) + iic(3,0x78,0x49,0x07,0x04); // e(Hi) + iic(2,0x78,0x48,0x01,0x00); // on=1 off=0 +#else + iic(3,0x78,0x49,0x00,0x95); // a + iic(3,0x78,0x49,0x01,0x96); // b + iic(3,0x78,0x49,0x03,0x85); // c + iic(3,0x78,0x49,0x04,0x97); // d + iic(3,0x78,0x49,0x02,0x7e); // e(Lo) + iic(3,0x78,0x49,0x05,0xa4); // f(Lo) + iic(3,0x78,0x49,0x06,0x04); // e(Hi) + iic(3,0x78,0x49,0x07,0x04); // e(Hi) + iic(2,0x78,0x48,0x01,0x00); // on=1 off=0 +#endif + + printk("."); + iic(2,0x78,0x11,0x00,0x00); // end + printk(" done\n"); + return 0; +} + + +void ar_release(struct video_device *vfd) +{ + struct ar_device *ar = vfd->priv; + down(&ar->lock); + video_device_release(vfd); +} + +/**************************************************************************** + * + * Video4Linux Module functions + * + ****************************************************************************/ +static struct file_operations ar_fops = { + .owner = THIS_MODULE, + .open = video_exclusive_open, + .release = video_exclusive_release, + .read = ar_read, + .ioctl = ar_ioctl, + .llseek = no_llseek, +}; + +static struct video_device ar_template = { + .owner = THIS_MODULE, + .name = "Colour AR VGA", + .type = VID_TYPE_CAPTURE, + .hardware = VID_HARDWARE_ARV, + .fops = &ar_fops, + .release = ar_release, + .minor = -1, +}; + +#define ALIGN4(x) ((((int)(x)) & 0x3) == 0) +static struct ar_device ardev; + +static int __init ar_init(void) +{ + struct ar_device *ar; + int ret; + int i; + + DEBUG(1, "ar_init:\n"); + ret = -EIO; + printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION); + + ar = &ardev; + memset(ar, 0, sizeof(struct ar_device)); + +#if USE_INT + /* allocate a DMA buffer for 1 line. */ + ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA); + if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) { + printk("arv: buffer allocation failed for DMA.\n"); + ret = -ENOMEM; + goto out_end; + } +#endif + /* allocate buffers for a frame */ + for (i = 0; i < MAX_AR_HEIGHT; i++) { + ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL); + if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) { + printk("arv: buffer allocation failed for frame.\n"); + ret = -ENOMEM; + goto out_line_buff; + } + } + + ar->vdev = video_device_alloc(); + if(!ar->vdev){ + printk(KERN_ERR "arv: video_device_alloc() failed\n"); + return -ENOMEM; + } + memcpy(ar->vdev, &ar_template, sizeof(ar_template)); + ar->vdev->priv = ar; + + if (vga) { + ar->width = AR_WIDTH_VGA; + ar->height = AR_HEIGHT_VGA; + ar->size = AR_SIZE_VGA; + ar->frame_bytes = AR_FRAME_BYTES_VGA; + ar->line_bytes = AR_LINE_BYTES_VGA; + if (vga_interlace) + ar->mode = AR_MODE_INTERLACE; + else + ar->mode = AR_MODE_NORMAL; + } else { + ar->width = AR_WIDTH_QVGA; + ar->height = AR_HEIGHT_QVGA; + ar->size = AR_SIZE_QVGA; + ar->frame_bytes = AR_FRAME_BYTES_QVGA; + ar->line_bytes = AR_LINE_BYTES_QVGA; + ar->mode = AR_MODE_INTERLACE; + } + init_MUTEX(&ar->lock); + init_waitqueue_head(&ar->wait); + +#if USE_INT + if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)){ + printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3); + ret = -EIO; + goto out_irq; + } +#endif + + if (ar_initialize(ar->vdev) != 0 ){ + printk("arv: M64278 not found.\n"); + ret = -ENODEV; + goto out_dev; + } + + /* + * ok, we can initialize h/w according to parameters, + * so register video device as a frame grabber type. + * device is named "video[0-64]". + * video_register_device() initializes h/w using ar_initialize(). + */ + if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr)!=0) { + /* return -1, -ENFILE(full) or others */ + printk("arv: register video (Colour AR) failed.\n"); + ret = -ENODEV; + goto out_dev; + } + + printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n", + ar->vdev->minor, M32R_IRQ_INT3, freq); + + return 0; + +out_dev: +#if USE_INT + free_irq(M32R_IRQ_INT3, ar); +out_irq: +#endif + for (i = 0; i < MAX_AR_HEIGHT; i++) + if (ar->frame[i]) kfree(ar->frame[i]); +out_line_buff: +#if USE_INT + kfree(ar->line_buff); +out_end: +#endif + return ret; +} + + +static int __init ar_init_module(void) +{ + freq = (boot_cpu_data.bus_clock / 1000000); + printk("arv: Bus clock %d\n", freq); + if (freq != 50 && freq != 75) + freq = DEFAULT_FREQ; + return ar_init(); +} + +static void __exit ar_cleanup_module(void) +{ + struct ar_device *ar; + int i; + + ar = &ardev; + video_unregister_device(ar->vdev); +#if USE_INT + free_irq(M32R_IRQ_INT3, ar); +#endif + for (i = 0; i < MAX_AR_HEIGHT; i++) + if (ar->frame[i]) kfree(ar->frame[i]); +#if USE_INT + kfree(ar->line_buff); +#endif +} + +module_init(ar_init_module); +module_exit(ar_cleanup_module); + +MODULE_AUTHOR("Takeo Takahashi "); +MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux"); +MODULE_LICENSE("GPL"); diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/media/video/arv.h linux-2.6.8.1/drivers/media/video/arv.h --- linux-2.6.8.1.org/drivers/media/video/arv.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/media/video/arv.h 2004-07-28 16:41:33.000000000 +0900 @@ -0,0 +1,384 @@ +/* + * include/asm/m32700.h + * + * Control registers and Special function registers of M32700 + * + * Copyright (c) 2003 Takeo Takahashi + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * $Id: arv.h,v 1.1 2004/07/28 07:41:33 fujiwara Exp $ + * + * 2003-08-26: Bug fixed. M32700_DMA0BCUT => M32700_DMA0CBCUT + * by Takeo Takahashi + * + */ + +#ifndef _M32700_H +#define _M32700_H + +#ifndef M32700_IAMOD +#define M32700_IAMOD 0 /* default IAMOD=0 */ +#endif + +#if M32700_IAMOD +#define M32700_IAMOD_SFR (0x03e00000) +#else +#define M32700_IAMOD_SFR (0x00e00000) +#endif + +#ifndef __ASSEMBLY__ +#define M32700_SFR_BASE (M32700_IAMOD_SFR) +#define __reg8 (volatile unsigned char *) +#define __reg16 (volatile unsigned short *) +#define __reg32 (volatile unsigned int *) +#else +#define M32700_SFR_BASE (M32700_IAMOD_SFR) +#define __reg8 +#define __reg16 +#define __reg32 +#endif /* __ASSEMBLY__ */ + +/************************************************* + * Control Registers accessed directly + *************************************************/ +/* + * Instruction TLB table + */ +#define M32700_ITBL_NUMS 32 +#define M32700_ITBL_BASE (0xfe000000) +#define M32700_DTBL_NUMS 32 +#define M32700_DTBL_BASE (0xfe000800) + +/* + * MMU + */ +#define M32700_MMU_BASE (0xffff0000) +#define M32700_MMU_MATM __reg32(M32700_MMU_BASE + 0x00000000) +#define M32700_MMU_MPSZ __reg32(M32700_MMU_BASE + 0x00000004) +#define M32700_MMU_MASID __reg32(M32700_MMU_BASE + 0x00000008) +#define M32700_MMU_MESTS __reg32(M32700_MMU_BASE + 0x0000000c) +#define M32700_MMU_MDEVA __reg32(M32700_MMU_BASE + 0x00000010) +#define M32700_MMU_MDEVP __reg32(M32700_MMU_BASE + 0x00000014) +#define M32700_MMU_MSVA __reg32(M32700_MMU_BASE + 0x00000020) +#define M32700_MMU_MTOP __reg32(M32700_MMU_BASE + 0x00000024) +#define M32700_MMU_MIDXI __reg32(M32700_MMU_BASE + 0x00000028) +#define M32700_MMU_MIDXD __reg32(M32700_MMU_BASE + 0x0000002c) + +/* + * Cache + */ +#define M32700_CACHE_BASE (0xfffffff0) +#define M32700_CACHE_MCICAR __reg32(M32700_CACHE_BASE + 0x00000000) +#define M32700_CACHE_MCDCAR __reg32(M32700_CACHE_BASE + 0x00000004) +#define M32700_CACHE_MCCR __reg32(M32700_CACHE_BASE + 0x0000000c) + +/* + * EIT + */ +#define M32700_EIT_RI (0x00000000) +#define M32700_EIT_EVB (0x00000000) /* this means offset */ +#define M32700_EIT_SBI __reg32(M32700_EIT_EVB + 0x00000010) +#define M32700_EIT_RIE __reg32(M32700_EIT_EVB + 0x00000020) +#define M32700_EIT_AE __reg32(M32700_EIT_EVB + 0x00000030) +#define M32700_EIT_TRAP0 __reg32(M32700_EIT_EVB + 0x00000040) +#define M32700_EIT_TRAP1 __reg32(M32700_EIT_EVB + 0x00000044) +#define M32700_EIT_TRAP2 __reg32(M32700_EIT_EVB + 0x00000048) +#define M32700_EIT_TRAP3 __reg32(M32700_EIT_EVB + 0x0000004c) +#define M32700_EIT_TRAP4 __reg32(M32700_EIT_EVB + 0x00000050) +#define M32700_EIT_TRAP5 __reg32(M32700_EIT_EVB + 0x00000054) +#define M32700_EIT_TRAP6 __reg32(M32700_EIT_EVB + 0x00000058) +#define M32700_EIT_TRAP7 __reg32(M32700_EIT_EVB + 0x0000005c) +#define M32700_EIT_TRAP8 __reg32(M32700_EIT_EVB + 0x00000060) +#define M32700_EIT_TRAP9 __reg32(M32700_EIT_EVB + 0x00000064) +#define M32700_EIT_TRAP10 __reg32(M32700_EIT_EVB + 0x00000068) +#define M32700_EIT_TRAP11 __reg32(M32700_EIT_EVB + 0x0000006c) +#define M32700_EIT_TRAP12 __reg32(M32700_EIT_EVB + 0x00000070) +#define M32700_EIT_TRAP13 __reg32(M32700_EIT_EVB + 0x00000074) +#define M32700_EIT_TRAP14 __reg32(M32700_EIT_EVB + 0x00000078) +#define M32700_EIT_TRAP15 __reg32(M32700_EIT_EVB + 0x0000007c) +#define M32700_EIT_EI __reg32(M32700_EIT_EVB + 0x00000080) +#define M32700_EIT_PIE __reg32(M32700_EIT_EVB + 0x00000100) +#define M32700_EIT_IACE __reg32(M32700_EIT_EVB + 0x00000110) +#define M32700_EIT_DACE __reg32(M32700_EIT_EVB + 0x00000110) +#define M32700_EIT_ITME __reg32(M32700_EIT_EVB + 0x00000120) +#define M32700_EIT_DTME __reg32(M32700_EIT_EVB + 0x00000120) + +/* + * Multi-Processor + */ +#define M32700_MP_BASE (0xffffffe0) +#define M32700_MP_CPUID __reg32(M32700_MP_BASE + 0x00000000) + +/************************************************* + * Special Function Registers accessed by io/out + *************************************************/ + +/* + * Programable Port + */ +#define M32700_P0IEN __reg8(M32700_SFR_BASE + 0x000f1000) +#define M32700_P1IEN __reg8(M32700_SFR_BASE + 0x000f1001) +#define M32700_P2IEN __reg8(M32700_SFR_BASE + 0x000f1002) +#define M32700_P3IEN __reg8(M32700_SFR_BASE + 0x000f1003) +#define M32700_P4IEN __reg8(M32700_SFR_BASE + 0x000f1004) +#define M32700_P5IEN __reg8(M32700_SFR_BASE + 0x000f1005) +#define M32700_P6IEN __reg8(M32700_SFR_BASE + 0x000f1006) +#define M32700_P7IEN __reg8(M32700_SFR_BASE + 0x000f1007) +#define M32700_P8IEN __reg8(M32700_SFR_BASE + 0x000f1008) + +#define M32700_P0DIR __reg8(M32700_SFR_BASE + 0x000f1010) +#define M32700_P1DIR __reg8(M32700_SFR_BASE + 0x000f1011) +#define M32700_P2DIR __reg8(M32700_SFR_BASE + 0x000f1012) +#define M32700_P3DIR __reg8(M32700_SFR_BASE + 0x000f1013) +#define M32700_P4DIR __reg8(M32700_SFR_BASE + 0x000f1014) +#define M32700_P5DIR __reg8(M32700_SFR_BASE + 0x000f1015) +#define M32700_P6DIR __reg8(M32700_SFR_BASE + 0x000f1016) +#define M32700_P7DIR __reg8(M32700_SFR_BASE + 0x000f1017) +#define M32700_P8DIR __reg8(M32700_SFR_BASE + 0x000f1018) + +#define M32700_P0PDCR __reg16(M32700_SFR_BASE + 0x000f1020) +#define M32700_P1PDCR __reg16(M32700_SFR_BASE + 0x000f1022) +#define M32700_P2PDCR __reg16(M32700_SFR_BASE + 0x000f1024) +#define M32700_P3PDCR __reg16(M32700_SFR_BASE + 0x000f1026) +#define M32700_P4PDCR __reg16(M32700_SFR_BASE + 0x000f1028) +#define M32700_P5PDCR __reg16(M32700_SFR_BASE + 0x000f102a) +#define M32700_P6PDCR __reg16(M32700_SFR_BASE + 0x000f102c) +#define M32700_P7PDCR __reg16(M32700_SFR_BASE + 0x000f102e) +#define M32700_P8PDCR __reg16(M32700_SFR_BASE + 0x000f1030) + +#define M32700_P0OCR __reg16(M32700_SFR_BASE + 0x000f1040) +#define M32700_P1OCR __reg16(M32700_SFR_BASE + 0x000f1042) +#define M32700_P2OCR __reg16(M32700_SFR_BASE + 0x000f1044) +#define M32700_P3OCR __reg16(M32700_SFR_BASE + 0x000f1046) +#define M32700_P4OCR __reg16(M32700_SFR_BASE + 0x000f1048) +#define M32700_P5OCR __reg16(M32700_SFR_BASE + 0x000f104a) +#define M32700_P6OCR __reg16(M32700_SFR_BASE + 0x000f104c) +#define M32700_P7OCR __reg16(M32700_SFR_BASE + 0x000f104e) +#define M32700_P8OCR __reg16(M32700_SFR_BASE + 0x000f1050) + +#define M32700_P0MOD __reg16(M32700_SFR_BASE + 0x000f1060) +#define M32700_P1MOD __reg16(M32700_SFR_BASE + 0x000f1062) +#define M32700_P2MOD __reg16(M32700_SFR_BASE + 0x000f1064) +#define M32700_P3MOD __reg16(M32700_SFR_BASE + 0x000f1066) +#define M32700_P4MOD __reg16(M32700_SFR_BASE + 0x000f1068) +#define M32700_P5MOD __reg16(M32700_SFR_BASE + 0x000f106a) +#define M32700_P6MOD __reg16(M32700_SFR_BASE + 0x000f106c) +#define M32700_P7MOD __reg16(M32700_SFR_BASE + 0x000f106e) +#define M32700_P8MOD __reg16(M32700_SFR_BASE + 0x000f1070) + +#define M32700_P0DATA __reg8(M32700_SFR_BASE + 0x000f1080) +#define M32700_P1DATA __reg8(M32700_SFR_BASE + 0x000f1081) +#define M32700_P2DATA __reg8(M32700_SFR_BASE + 0x000f1082) +#define M32700_P3DATA __reg8(M32700_SFR_BASE + 0x000f1083) +#define M32700_P4DATA __reg8(M32700_SFR_BASE + 0x000f1084) +#define M32700_P5DATA __reg8(M32700_SFR_BASE + 0x000f1085) +#define M32700_P6DATA __reg8(M32700_SFR_BASE + 0x000f1086) +#define M32700_P7DATA __reg8(M32700_SFR_BASE + 0x000f1087) +#define M32700_P8DATA __reg8(M32700_SFR_BASE + 0x000f1088) + +/* + * ICU + */ +#define M32700_ICUISTS __reg32(M32700_SFR_BASE + 0x000ff004) +#define M32700_ICUIREQ0 __reg32(M32700_SFR_BASE + 0x000ff008) +#define M32700_ICUIREQ1 __reg32(M32700_SFR_BASE + 0x000ff00c) + +#define M32700_ICUSBICR __reg32(M32700_SFR_BASE + 0x000ff018) +#define M32700_ICUIMASK __reg32(M32700_SFR_BASE + 0x000ff01c) + +#define M32700_ICUCR1 __reg32(M32700_SFR_BASE + 0x000ff200) +#define M32700_ICUCR2 __reg32(M32700_SFR_BASE + 0x000ff204) +#define M32700_ICUCR3 __reg32(M32700_SFR_BASE + 0x000ff208) +#define M32700_ICUCR4 __reg32(M32700_SFR_BASE + 0x000ff20c) +#define M32700_ICUCR5 __reg32(M32700_SFR_BASE + 0x000ff210) +#define M32700_ICUCR6 __reg32(M32700_SFR_BASE + 0x000ff214) +#define M32700_ICUCR7 __reg32(M32700_SFR_BASE + 0x000ff218) +#define M32700_ICUCR8 __reg32(M32700_SFR_BASE + 0x000ff21c) +#define M32700_ICUCR16 __reg32(M32700_SFR_BASE + 0x000ff23c) +#define M32700_ICUCR17 __reg32(M32700_SFR_BASE + 0x000ff24c) +#define M32700_ICUCR18 __reg32(M32700_SFR_BASE + 0x000ff244) +#define M32700_ICUCR19 __reg32(M32700_SFR_BASE + 0x000ff248) +#define M32700_ICUCR20 __reg32(M32700_SFR_BASE + 0x000ff24c) +#define M32700_ICUCR21 __reg32(M32700_SFR_BASE + 0x000ff250) +#define M32700_ICUCR32 __reg32(M32700_SFR_BASE + 0x000ff27c) +#define M32700_ICUCR33 __reg32(M32700_SFR_BASE + 0x000ff280) +#define M32700_ICUCR48 __reg32(M32700_SFR_BASE + 0x000ff2bc) +#define M32700_ICUCR49 __reg32(M32700_SFR_BASE + 0x000ff2c0) +#define M32700_ICUCR50 __reg32(M32700_SFR_BASE + 0x000ff2c4) +#define M32700_ICUCR51 __reg32(M32700_SFR_BASE + 0x000ff2c8) + +#define M32700_WKUPCR __reg32(M32700_SFR_BASE + 0x000ff2d8) +#define M32700_IPICR0 __reg32(M32700_SFR_BASE + 0x000ff2dc) +#define M32700_IPICR1 __reg32(M32700_SFR_BASE + 0x000ff2e0) +#define M32700_IPICR2 __reg32(M32700_SFR_BASE + 0x000ff2e4) +#define M32700_IPICR3 __reg32(M32700_SFR_BASE + 0x000ff2e8) +#define M32700_IPICR4 __reg32(M32700_SFR_BASE + 0x000ff2ec) +#define M32700_IPICR5 __reg32(M32700_SFR_BASE + 0x000ff2f0) +#define M32700_IPICR6 __reg32(M32700_SFR_BASE + 0x000ff2f4) +#define M32700_IPICR7 __reg32(M32700_SFR_BASE + 0x000ff2f8) + +/* + * Block Select Controller + */ +#define M32700_BSEL0CR0 __reg32(M32700_SFR_BASE + 0x000f5000) +#define M32700_BSEL1CR0 __reg32(M32700_SFR_BASE + 0x000f5100) +#define M32700_BSEL2CR0 __reg32(M32700_SFR_BASE + 0x000f5200) +#define M32700_BSEL3CR0 __reg32(M32700_SFR_BASE + 0x000f5300) +#define M32700_BSEL4CR0 __reg32(M32700_SFR_BASE + 0x000f5400) +#define M32700_BSEL5CR0 __reg32(M32700_SFR_BASE + 0x000f5500) +#define M32700_BSEL6CR0 __reg32(M32700_SFR_BASE + 0x000f5600) +#define M32700_BSEL7CR0 __reg32(M32700_SFR_BASE + 0x000f5700) + +#define M32700_BSEL0CR1 __reg32(M32700_SFR_BASE + 0x000f5004) +#define M32700_BSEL1CR1 __reg32(M32700_SFR_BASE + 0x000f5104) +#define M32700_BSEL2CR1 __reg32(M32700_SFR_BASE + 0x000f5204) +#define M32700_BSEL3CR1 __reg32(M32700_SFR_BASE + 0x000f5304) +#define M32700_BSEL4CR1 __reg32(M32700_SFR_BASE + 0x000f5404) +#define M32700_BSEL5CR1 __reg32(M32700_SFR_BASE + 0x000f5504) +#define M32700_BSEL6CR1 __reg32(M32700_SFR_BASE + 0x000f5604) +#define M32700_BSEL7CR1 __reg32(M32700_SFR_BASE + 0x000f5704) + +/* + * SDRAMC + */ +#define M32700_SDRF0 __reg32(M32700_SFR_BASE + 0x000f6000) +#define M32700_SDRF1 __reg32(M32700_SFR_BASE + 0x000f6004) +#define M32700_SDIR0 __reg32(M32700_SFR_BASE + 0x000f6008) +#define M32700_SDIR1 __reg32(M32700_SFR_BASE + 0x000f600c) + +#define M32700_SD0ADR __reg32(M32700_SFR_BASE + 0x000f6020) +#define M32700_SD0ER __reg32(M32700_SFR_BASE + 0x000f6024) +#define M32700_SD0TR __reg32(M32700_SFR_BASE + 0x000f6028) +#define M32700_SD0MOD __reg32(M32700_SFR_BASE + 0x000f602c) + +#define M32700_SD1ADR __reg32(M32700_SFR_BASE + 0x000f6040) +#define M32700_SD1ER __reg32(M32700_SFR_BASE + 0x000f6044) +#define M32700_SD1TR __reg32(M32700_SFR_BASE + 0x000f6048) +#define M32700_SD1MOD __reg32(M32700_SFR_BASE + 0x000f604c) + +/* + * PCC + */ +#define M32700_PCCR __reg32(M32700_SFR_BASE + 0x000f7000) +#define M32700_PCADR __reg32(M32700_SFR_BASE + 0x000f7004) +#define M32700_PCMOD __reg32(M32700_SFR_BASE + 0x000f7008) +#define M32700_PCIRC __reg32(M32700_SFR_BASE + 0x000f700c) +#define M32700_PCCSIGCR __reg32(M32700_SFR_BASE + 0x000f7010) +#define M32700_PCATCR __reg32(M32700_SFR_BASE + 0x000f7014) + +/* + * DMAC + */ +#define M32700_DMAEN __reg32(M32700_SFR_BASE + 0x000f8000) +#define M32700_DMAISTS __reg32(M32700_SFR_BASE + 0x000f8004) +#define M32700_DMAEDET __reg32(M32700_SFR_BASE + 0x000f8008) +#define M32700_DMAASTS __reg32(M32700_SFR_BASE + 0x000f800c) + +#define M32700_DMA0CR0 __reg32(M32700_SFR_BASE + 0x000f8100) +#define M32700_DMA0CR1 __reg32(M32700_SFR_BASE + 0x000f8104) +#define M32700_DMA0CSA __reg32(M32700_SFR_BASE + 0x000f8108) +#define M32700_DMA0RSA __reg32(M32700_SFR_BASE + 0x000f810c) +#define M32700_DMA0CDA __reg32(M32700_SFR_BASE + 0x000f8110) +#define M32700_DMA0RDA __reg32(M32700_SFR_BASE + 0x000f8114) +#define M32700_DMA0CBCUT __reg32(M32700_SFR_BASE + 0x000f8118) +#define M32700_DMA0RBCUT __reg32(M32700_SFR_BASE + 0x000f811c) + +#define M32700_DMA1CR0 __reg32(M32700_SFR_BASE + 0x000f8200) +#define M32700_DMA1CR1 __reg32(M32700_SFR_BASE + 0x000f8204) +#define M32700_DMA1CSA __reg32(M32700_SFR_BASE + 0x000f8208) +#define M32700_DMA1RSA __reg32(M32700_SFR_BASE + 0x000f820c) +#define M32700_DMA1CDA __reg32(M32700_SFR_BASE + 0x000f8210) +#define M32700_DMA1RDA __reg32(M32700_SFR_BASE + 0x000f8214) +#define M32700_DMA1CBCUT __reg32(M32700_SFR_BASE + 0x000f8218) +#define M32700_DMA1RBCUT __reg32(M32700_SFR_BASE + 0x000f821c) + +/* + * MFT + */ +#define M32700_MFTCR __reg32(M32700_SFR_BASE + 0x000fc000) +#define M32700_MFTRPR __reg32(M32700_SFR_BASE + 0x000fc004) + +#define M32700_MFT0MOD __reg32(M32700_SFR_BASE + 0x000fc100) +#define M32700_MFT0OS __reg32(M32700_SFR_BASE + 0x000fc104) +#define M32700_MFT0CUT __reg32(M32700_SFR_BASE + 0x000fc108) +#define M32700_MFT0RLD __reg32(M32700_SFR_BASE + 0x000fc10c) +#define M32700_MFT0CMPRLD __reg32(M32700_SFR_BASE + 0x000fc110) + +#define M32700_MFT1MOD __reg32(M32700_SFR_BASE + 0x000fc200) +#define M32700_MFT1OS __reg32(M32700_SFR_BASE + 0x000fc204) +#define M32700_MFT1CUT __reg32(M32700_SFR_BASE + 0x000fc208) +#define M32700_MFT1RLD __reg32(M32700_SFR_BASE + 0x000fc20c) +#define M32700_MFT1CMPRLD __reg32(M32700_SFR_BASE + 0x000fc210) + +#define M32700_MFT2MOD __reg32(M32700_SFR_BASE + 0x000fc300) +#define M32700_MFT2OS __reg32(M32700_SFR_BASE + 0x000fc304) +#define M32700_MFT2CUT __reg32(M32700_SFR_BASE + 0x000fc308) +#define M32700_MFT2RLD __reg32(M32700_SFR_BASE + 0x000fc30c) +#define M32700_MFT2CMPRLD __reg32(M32700_SFR_BASE + 0x000fc310) + +#define M32700_MFT3MOD __reg32(M32700_SFR_BASE + 0x000fc400) +#define M32700_MFT3OS __reg32(M32700_SFR_BASE + 0x000fc404) +#define M32700_MFT3CUT __reg32(M32700_SFR_BASE + 0x000fc408) +#define M32700_MFT3RLD __reg32(M32700_SFR_BASE + 0x000fc40c) +#define M32700_MFT3CMPRLD __reg32(M32700_SFR_BASE + 0x000fc410) + +#define M32700_MFT4MOD __reg32(M32700_SFR_BASE + 0x000fc500) +#define M32700_MFT4OS __reg32(M32700_SFR_BASE + 0x000fc504) +#define M32700_MFT4CUT __reg32(M32700_SFR_BASE + 0x000fc508) +#define M32700_MFT4RLD __reg32(M32700_SFR_BASE + 0x000fc50c) +#define M32700_MFT4CMPRLD __reg32(M32700_SFR_BASE + 0x000fc510) + +#define M32700_MFT5MOD __reg32(M32700_SFR_BASE + 0x000fc600) +#define M32700_MFT5OS __reg32(M32700_SFR_BASE + 0x000fc604) +#define M32700_MFT5CUT __reg32(M32700_SFR_BASE + 0x000fc608) +#define M32700_MFT5RLD __reg32(M32700_SFR_BASE + 0x000fc60c) +#define M32700_MFT5CMPRLD __reg32(M32700_SFR_BASE + 0x000fc610) + +/* + * SIO + */ +#define M32700_SIO0CR __reg32(M32700_SFR_BASE + 0x000fd000) +#define M32700_SIO0MOD0 __reg32(M32700_SFR_BASE + 0x000fd004) +#define M32700_SIO0MOD1 __reg32(M32700_SFR_BASE + 0x000fd008) +#define M32700_SIO0STS __reg32(M32700_SFR_BASE + 0x000fd00c) +#define M32700_SIO0TRCR __reg32(M32700_SFR_BASE + 0x000fd010) +#define M32700_SIO0BAUR __reg32(M32700_SFR_BASE + 0x000fd014) +#define M32700_SIO0RBAUR __reg32(M32700_SFR_BASE + 0x000fd018) +#define M32700_SIO0TXB __reg32(M32700_SFR_BASE + 0x000fd01c) +#define M32700_SIO0RXB __reg32(M32700_SFR_BASE + 0x000fd020) + +#define M32700_SIO1CR __reg32(M32700_SFR_BASE + 0x000fd100) +#define M32700_SIO1MOD0 __reg32(M32700_SFR_BASE + 0x000fd104) +#define M32700_SIO1MOD1 __reg32(M32700_SFR_BASE + 0x000fd108) +#define M32700_SIO1STS __reg32(M32700_SFR_BASE + 0x000fd10c) +#define M32700_SIO1TRCR __reg32(M32700_SFR_BASE + 0x000fd110) +#define M32700_SIO1BAUR __reg32(M32700_SFR_BASE + 0x000fd114) +#define M32700_SIO1RBAUR __reg32(M32700_SFR_BASE + 0x000fd118) +#define M32700_SIO1TXB __reg32(M32700_SFR_BASE + 0x000fd11c) +#define M32700_SIO1RXB __reg32(M32700_SFR_BASE + 0x000fd120) + +/* + * WDT + */ +#define M32700_WDTCR __reg32(M32700_SFR_BASE + 0x000f2000) + +/* + * Clock + */ +#define M32700_PLLCR __reg32(M32700_SFR_BASE + 0x000f4004) +#define M32700_MASTERCR __reg32(M32700_SFR_BASE + 0x000f4008) +#define M32700_CPU0DIV __reg32(M32700_SFR_BASE + 0x000f4010) +#define M32700_CPU1DIV __reg32(M32700_SFR_BASE + 0x000f4014) +#define M32700_BIFDIV __reg32(M32700_SFR_BASE + 0x000f4020) +#define M32700_BCLKDIV __reg32(M32700_SFR_BASE + 0x000f4024) +#define M32700_FCLKSEL __reg32(M32700_SFR_BASE + 0x000f4028) +#define M32700_CPU0STOP __reg32(M32700_SFR_BASE + 0x000f4030) +#define M32700_CPU1STOP __reg32(M32700_SFR_BASE + 0x000f4034) +#define M32700_STNBY __reg32(M32700_SFR_BASE + 0x000f404c) +#define M32700_CDIVST __reg32(M32700_SFR_BASE + 0x000f4050) + +#endif /* _M32700_H */ diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/mtd/maps/Makefile linux-2.6.8.1/drivers/mtd/maps/Makefile --- linux-2.6.8.1.org/drivers/mtd/maps/Makefile 2004-08-14 19:54:46.000000000 +0900 +++ linux-2.6.8.1/drivers/mtd/maps/Makefile 2004-08-30 10:24:01.000000000 +0900 @@ -64,3 +64,5 @@ obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o obj-$(CONFIG_MTD_DMV182) += dmv182.o + +obj-$(CONFIG_MTD_M32R) += m32r-flash.o diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/mtd/maps/m32r-flash.c linux-2.6.8.1/drivers/mtd/maps/m32r-flash.c --- linux-2.6.8.1.org/drivers/mtd/maps/m32r-flash.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/mtd/maps/m32r-flash.c 2004-08-30 10:24:01.000000000 +0900 @@ -0,0 +1,247 @@ +/* + * Flash memory access on M32R based devices + * + * Copyright (C) 2003 Takeo Takahashi, Hitoshi Yamamoto + * Takeshi Aoki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * $Id$ + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#define WINDOW_ADDR (0x00000000) /* start of flash memory */ + +static struct map_info m32r_map = { + .name = "M32R flash", + .bankwidth = 2, + .phys = WINDOW_ADDR, +}; + +static int flash_write = 0; + +static int __init flash_write_setup(char *str) +{ + flash_write = 1; + printk("Flash ROM write enabled\n"); + return 1; +} + +__setup("flash_write", flash_write_setup); + +#if defined(CONFIG_PLAT_M32700UT) +#define M32700UT_FLASH_SIZE 0x00800000 +static struct mtd_partition m32700ut_partitions[] = { + { + .name = "M32700UT boot firmware", + .size = 0x30000, /* 192KB */ + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "M32700UT kernel", + .size = 0xd0000, /* 832KB */ + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "M32700UT root", + .size = 0x6f0000, /* 7104KB */ + .offset = MTDPART_OFS_APPEND, + }, { + .name = "M32700UT params", + .size = MTDPART_SIZ_FULL, /* 64KB */ + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + } +}; +#elif defined(CONFIG_PLAT_MAPPI2) +#define M32700UT_FLASH_SIZE 0x00400000 +static struct mtd_partition m32700ut_partitions[] = { + { + .name = "M3A-ZA36 boot firmware", + .size = 0x30000, /* 192KB */ + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "M3A-ZA36 kernel", + .size = 0xd0000, /* 832KB */ + .offset = MTDPART_OFS_APPEND, + }, { + .name = "M3A-ZA36 root", + .size = 0x2f0000, /* 3008KB */ + .offset = MTDPART_OFS_APPEND, + }, { + .name = "M3A-ZA36 params", + .size = MTDPART_SIZ_FULL, /* 64KB */ + .offset = MTDPART_OFS_APPEND, + } +}; +#elif defined(CONFIG_PLAT_USRV) +#define USRV_FLASH_SIZE 0x00800000 +/* + * chip : MBM29DL640E (Fujitsu) + * phys addr : 0x00000000 + * size : 0x00800000 (8MB) + * 0x00000000 - 0x0000ffff : 8KB sector : 64KB + * 0x00010000 - 0x007effff : 64KB sector : 8064KB + * 0x007f0000 - 0x007fffff : 8KB sector : 64KB + */ + +static struct mtd_partition usrv_partitions[] = { + { + .name = "Boot loader", + .size = 0xe000, /* 56KB */ + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "Kernel parameter", + .size = 0x2000, /* 8KB */ + .offset = MTDPART_OFS_APPEND, + }, { + .name = "Kernel", + .size = 0x200000, /* 2MB */ + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "INITRD", + .size = 0xe0000, /* 896KB */ + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "User FS", + .size = 0x500000, /* 5MB */ + .offset = MTDPART_OFS_APPEND, + }, { + .name = "User parameter", + .size = 0x10000, /* 64KB */ + .offset = MTDPART_OFS_APPEND, + } +}; +#else +#error no platform configuration +#endif + +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition *parsed_parts; +const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; +#endif /* CONFIG_MTD_PARTITIONS */ +static struct mtd_info *mymtd; + +static int __init m32r_mtd_init(void) +{ + struct mtd_partition *parts; + int nb_parts = 0; + int parsed_nr_parts = 0; + const char *part_type; + + /* + * Static partition definition selection + */ + part_type = "static"; + +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) + parts = m32700ut_partitions; + nb_parts = ARRAY_SIZE(m32700ut_partitions); + m32r_map.size = M32700UT_FLASH_SIZE; + m32r_map.bankwidth = 2; +#elif defined(CONFIG_PLAT_USRV) + parts = usrv_partitions; + nb_parts = ARRAY_SIZE(usrv_partitions); + m32r_map.size = USRV_FLASH_SIZE; + m32r_map.bankwidth = 2; + { + int i; + + if (flash_write) + for (i = 0 ; i < nb_parts ; i++) + parts[i].mask_flags = 0; + } +#endif + + m32r_map.virt = (unsigned long)ioremap(WINDOW_ADDR, m32r_map.size); + if (!m32r_map.virt) { + printk("M32R flash: Failed to ioremap\n"); + return -EIO; + } + + simple_map_init(&m32r_map); + + /* + * Now let's probe for the actual flash. Do it here since + * specific machine settings might have been set above. + */ + printk(KERN_NOTICE "M32R flash: probing %d-bit flash bus\n", + m32r_map.bankwidth * 8); + +#ifdef CONFIG_MTD_M5 + mymtd = do_map_probe("m5drv", &m32r_map); +#elif CONFIG_MTD_CFI + mymtd = do_map_probe("cfi_probe", &m32r_map); +#else + mymtd = NULL; +#endif + if (!mymtd) { + iounmap((void *)m32r_map.virt); + return -ENXIO; + } + + mymtd->owner = THIS_MODULE; + + /* + * Dynamic partition selection stuff (might override the static ones) + */ +#ifdef CONFIG_MTD_PARTITIONS + parsed_nr_parts = parse_mtd_partitions(mymtd, part_probes, + &parsed_parts, 0); + if (parsed_nr_parts > 0) { + part_type = "dynamic"; + parts = parsed_parts; + nb_parts = parsed_nr_parts; + } +#endif /* CONFIG_MTD_PARTITIONS */ + + if (nb_parts == 0) { + printk(KERN_NOTICE "M32R flash: no partition info available," \ + " registering whole flash at once\n"); + add_mtd_device(mymtd); + } else { + printk(KERN_NOTICE "Using %s partition definition\n", + part_type); + add_mtd_partitions(mymtd, parts, nb_parts); + } + + return 0; +} + +static void __exit m32r_mtd_cleanup(void) +{ + if (mymtd) { + del_mtd_partitions(mymtd); + map_destroy(mymtd); + } + if (m32r_map.virt) { + iounmap((void *)m32r_map.virt); + m32r_map.virt = 0; + } +} + +module_init(m32r_mtd_init); +module_exit(m32r_mtd_cleanup); + +MODULE_AUTHOR("Takeo Takahashi"); +MODULE_DESCRIPTION("M32R Flash map driver"); +MODULE_LICENSE("GPL"); diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/net/8390.c linux-2.6.8.1/drivers/net/8390.c --- linux-2.6.8.1.org/drivers/net/8390.c 2004-08-14 19:54:50.000000000 +0900 +++ linux-2.6.8.1/drivers/net/8390.c 2004-07-15 13:43:15.000000000 +0900 @@ -213,6 +213,16 @@ void ei_tx_timeout(struct net_device *dev) { +#if defined(CONFIG_M32R) && defined(CONFIG_SMP) /* WORKAROUND : lost interrupt */ + unsigned long flags, icucr; + + printk(KERN_DEBUG "%s : timeout\n", dev->name); + local_irq_save(flags); + icucr = inl(0x00eff200); + icucr |= 0x00000030; + outl(icucr, 0x00eff200); + local_irq_restore(flags); +#else /* WORKAROUND */ long e8390_base = dev->base_addr; struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev); int txsr, isr, tickssofar = jiffies - dev->trans_start; @@ -247,6 +257,7 @@ spin_unlock(&ei_local->page_lock); enable_irq(dev->irq); netif_wake_queue(dev); +#endif /* WORKAROUND */ } /** diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/net/Space.c linux-2.6.8.1/drivers/net/Space.c --- linux-2.6.8.1.org/drivers/net/Space.c 2004-08-14 19:54:49.000000000 +0900 +++ linux-2.6.8.1/drivers/net/Space.c 2004-08-30 10:24:01.000000000 +0900 @@ -93,7 +93,10 @@ extern struct net_device *mc32_probe(int unit); extern struct net_device *cops_probe(int unit); extern struct net_device *ltpc_probe(void); - +#ifdef CONFIG_M32R_SMC91111 +extern struct net_device *m32r_smc_init(int unit); +#endif /* CONFIG_M32R_SMC91111 */ + /* Detachable devices ("pocket adaptors") */ extern struct net_device *de620_probe(int unit); @@ -192,9 +195,12 @@ {e2100_probe, 0}, #endif #if defined(CONFIG_NE2000) || \ - defined(CONFIG_NE_H8300) /* ISA (use ne2k-pci for PCI cards) */ + defined(CONFIG_NE_H8300) || defined(CONFIG_M32R_NE2000) /* ISA (use ne2k-pci for PCI cards) */ {ne_probe, 0}, #endif +#ifdef CONFIG_M32R_SMC91111 /* SMC91111 for M32R */ + {m32r_smc_init, 0}, +#endif #ifdef CONFIG_LANCE /* ISA/VLB (use pcnet32 for PCI cards) */ {lance_probe, 0}, #endif diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/net/wireless/hermes.h linux-2.6.8.1/drivers/net/wireless/hermes.h --- linux-2.6.8.1.org/drivers/net/wireless/hermes.h 2004-08-14 19:54:48.000000000 +0900 +++ linux-2.6.8.1/drivers/net/wireless/hermes.h 2004-07-15 13:43:15.000000000 +0900 @@ -299,6 +299,17 @@ } hermes_response_t; /* Register access convenience macros */ +#if defined(__m32r__) +#define hermes_read_reg(hw, off) ((hw)->io_space ? \ + le16_to_cpu(inw((hw)->iobase + ( (off) << (hw)->reg_spacing ))) : \ + readw((hw)->iobase + ( (off) << (hw)->reg_spacing ))) +#define hermes_write_reg(hw, off, val) do { \ + if ((hw)->io_space) \ + outw_p(cpu_to_le16((val)), (hw)->iobase + ((off) << (hw)->reg_spacing)); \ + else \ + writew((val), (hw)->iobase + ((off) << (hw)->reg_spacing)); \ + } while (0) +#else /* !__m32r__ */ #define hermes_read_reg(hw, off) ((hw)->io_space ? \ inw((hw)->iobase + ( (off) << (hw)->reg_spacing )) : \ readw((hw)->iobase + ( (off) << (hw)->reg_spacing ))) @@ -308,6 +319,7 @@ else \ writew((val), (hw)->iobase + ((off) << (hw)->reg_spacing)); \ } while (0) +#endif /* !__m32r__ */ #define hermes_read_regn(hw, name) hermes_read_reg((hw), HERMES_##name) #define hermes_write_regn(hw, name, val) hermes_write_reg((hw), HERMES_##name, (val)) diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/Kconfig linux-2.6.8.1/drivers/serial/Kconfig --- linux-2.6.8.1.org/drivers/serial/Kconfig 2004-08-14 19:56:22.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/Kconfig 2004-08-30 10:24:02.000000000 +0900 @@ -595,6 +595,28 @@ on your PowerMac as the console, you can do so by answering Y to this option. +config SERIAL_M32R_SIO + bool "M32R SIO I/F" + depends on M32R + default y + select SERIAL_CORE + +config SERIAL_M32R_SIO_CONSOLE + bool "use SIO console" + depends on SERIAL_M32R_SIO=y + select SERIAL_CORE_CONSOLE + +config SERIAL_M32R_PLDSIO + bool "M32R PLD SIO I/F" + depends on M32R + default y + select SERIAL_CORE + +config SERIAL_M32R_PLDSIO_CONSOLE + bool "use PLD SIO console" + depends on SERIAL_M32R_PLDSIO=y + select SERIAL_CORE_CONSOLE + config SERIAL_LH7A40X tristate "Sharp LH7A40X embedded UART support" depends on ARM && ARCH_LH7A40X diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/Makefile linux-2.6.8.1/drivers/serial/Makefile --- linux-2.6.8.1.org/drivers/serial/Makefile 2004-08-14 19:55:32.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/Makefile 2004-08-30 10:24:02.000000000 +0900 @@ -41,3 +41,6 @@ obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o obj-$(CONFIG_SERIAL_CPM) += cpm_uart/ obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o + +obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o +obj-$(CONFIG_SERIAL_M32R_PLDSIO) += m32r-pld_sio.o diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/m32r-pld_sio.c linux-2.6.8.1/drivers/serial/m32r-pld_sio.c --- linux-2.6.8.1.org/drivers/serial/m32r-pld_sio.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/m32r-pld_sio.c 2004-08-30 10:24:02.000000000 +0900 @@ -0,0 +1,1283 @@ +/* + * linux/drivers/char/8250.c + * + * Driver for 8250/16550-type serial ports + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright (C) 2001 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * $Id: m32r-pld_sio.c,v 1.2 2004/02/04 08:10:41 fujiwara Exp $ + * + * A note about mapbase / membase + * + * mapbase is the physical address of the IO port. Currently, we don't + * support this very well, and it may well be dropped from this driver + * in future. As such, mapbase should be NULL. + * + * membase is an 'ioremapped' cookie. This is compatible with the old + * serial.c driver, and is currently the preferred form. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#if defined(CONFIG_SERIAL_M32R_PLDSIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#define PORT_SIO 1 +#define PORT_MAX_SIO 1 +#define BAUD_RATE 115200 + +#include +#include "m32r-pld_sio.h" +#include "m32r-pld_sio_reg.h" + +/* + * Configuration: + * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option + * is unsafe when used on edge-triggered interrupts. + */ +unsigned int share_irqs_pldsio = SERIALPLDSIO_SHARE_IRQS; + +/* + * Debugging. + */ +#if 0 +#define DEBUG_AUTOCONF(fmt...) printk(fmt) +#else +#define DEBUG_AUTOCONF(fmt...) do { } while (0) +#endif + +#if 0 +#define DEBUG_INTR(fmt...) printk(fmt) +#else +#define DEBUG_INTR(fmt...) do { } while (0) +#endif + +#define PASS_LIMIT 256 + +/* + * We default to IRQ0 for the "no irq" hack. Some + * machine types want others as well - they're free + * to redefine this in their header file. + */ +#define is_real_interrupt(irq) ((irq) != 0) + +/* + * This converts from our new CONFIG_ symbols to the symbols + * that asm/serial.h expects. You _NEED_ to comment out the + * linux/config.h include contained inside asm/serial.h for + * this to work. + */ +#undef CONFIG_SERIAL_MANY_PORTS +#undef CONFIG_SERIAL_DETECT_IRQ +#undef CONFIG_SERIAL_MULTIPORT +#undef CONFIG_HUB6 + +#ifdef CONFIG_SERIAL_M32R_PLDSIO_DETECT_IRQ +#define CONFIG_SERIAL_DETECT_IRQ 1 +#endif +#ifdef CONFIG_SERIAL_M32R_PLDSIO_MULTIPORT +#define CONFIG_SERIAL_MULTIPORT 1 +#endif +#ifdef CONFIG_SERIAL_M32R_PLDSIO_MANY_PORTS +#define CONFIG_SERIAL_MANY_PORTS 1 +#endif + +/* + * HUB6 is always on. This will be removed once the header + * files have been cleaned. + */ +#define CONFIG_HUB6 1 + +#include + +static struct old_serial_port old_serial_port[] = { + { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, STD_COM_FLAGS }, +}; + +#define UART_NR ARRAY_SIZE(old_serial_port) + +struct uart_pldsio_port { + struct uart_port port; + struct timer_list timer; /* "no irq" timer */ + struct list_head list; /* ports on this IRQ */ + unsigned short rev; + unsigned char acr; + unsigned char ier; + unsigned char lcr; + unsigned char mcr_mask; /* mask of user bits */ + unsigned char mcr_force; /* mask of forced bits */ + unsigned char lsr_break_flag; + + /* + * We provide a per-port pm hook. + */ + void (*pm)(struct uart_port *port, + unsigned int state, unsigned int old); +}; + +struct irq_info { + spinlock_t lock; + struct list_head *head; +}; + +static struct irq_info irq_lists[NR_IRQS]; + +/* + * Here we define the default xmit fifo size used for each type of UART. + */ +static const struct serial_uart_config uart_config[PORT_MAX_SIO+1] = { + { "unknown", 1, 0 }, + { "M32RPLDSIO", 1, 0 } +}; + +static void pldsio_reset(void) +{ + unsigned short dummy,baud; + + dummy=inw((unsigned long)PLD_ESIO0RXB); + dummy=inw((unsigned long)PLD_ESIO0RXB); + dummy=inw((unsigned long)PLD_ESIO0CR); + baud = (boot_cpu_data.bus_clock / (BAUD_RATE * 4))-1; + outw(baud, (unsigned long)PLD_ESIO0BAUR); + outw(0x0300, (unsigned long)PLD_ESIO0CR); + outw(0x0003, (unsigned long)PLD_ESIO0CR); +} + +static void pldsio_init(void) +{ + unsigned short dummy; + + dummy=inw((unsigned long)PLD_ESIO0RXB); + dummy=inw((unsigned long)PLD_ESIO0RXB); + dummy=inw((unsigned long)PLD_ESIO0CR); + outw(0x0300, (unsigned long)PLD_ESIO0CR); + outw(0x0003, (unsigned long)PLD_ESIO0CR); +} + +static void pldsio_error(int *status) +{ + printk("PLDSIO0 error[%04x]\n", *status); + do { + pldsio_init(); + } while ((*status = inw((unsigned long)PLD_ESIO0CR)) != 3); +} + +static _INLINE_ unsigned int pldsio_in(struct uart_pldsio_port *up, int offset) +{ + return inw(up->port.iobase + offset); +} + +static _INLINE_ void pldsio_out(struct uart_pldsio_port *up, int offset, int value) +{ + outw(value, up->port.iobase + offset); +} + +static _INLINE_ unsigned int serial_in(struct uart_pldsio_port *up, int offset) +{ + if (!offset) + return 0; + + return inw(offset); +} + +static _INLINE_ void +serial_out(struct uart_pldsio_port *up, int offset, int value) +{ + if (!offset) + return; + + outw(value, offset); +} + +/* + * We used to support using pause I/O for certain machines. We + * haven't supported this for a while, but just in case it's badly + * needed for certain old 386 machines, I've left these #define's + * in.... + */ +#define serial_inp(up, offset) serial_in(up, offset) +#define serial_outp(up, offset, value) serial_out(up, offset, value) + +static void serialpldsio_stop_tx(struct uart_port *port, unsigned int tty_stop) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + + if (up->ier & UART_IER_THRI) { + up->ier &= ~UART_IER_THRI; + serial_out(up, (unsigned long)UART_IER, up->ier); + } +} + +static void serialpldsio_start_tx(struct uart_port *port, unsigned int tty_start) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + struct circ_buf *xmit = &up->port.info->xmit; + + if (!(up->ier & UART_IER_THRI)) { + up->ier |= UART_IER_THRI; + serial_out(up, (unsigned long)UART_IER, up->ier); + serial_out(up, (unsigned long)UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + } + while((serial_in(up,(unsigned long)UART_LSR) & UART_EMPTY) != UART_EMPTY); +} + +static void serialpldsio_stop_rx(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + + up->ier &= ~UART_IER_RLSI; + up->port.read_status_mask &= ~UART_LSR_DR; + serial_out(up, (unsigned long)UART_IER, up->ier); +} + +static void serialpldsio_enable_ms(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + + up->ier |= UART_IER_MSI; + serial_out(up, (unsigned long)UART_IER, up->ier); +} + +static _INLINE_ void receive_chars(struct uart_pldsio_port *up, int *status, + struct pt_regs *regs) +{ + struct tty_struct *tty = up->port.info->tty; + unsigned char ch; + int max_count = 256; + + do { + if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { + tty->flip.work.func((void *)tty); + if (tty->flip.count >= TTY_FLIPBUF_SIZE) + return; // if TTY_DONT_FLIP is set + } + ch = pldsio_in(up, SIORXB); + *tty->flip.char_buf_ptr = ch; + *tty->flip.flag_buf_ptr = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | + UART_LSR_FE | UART_LSR_OE))) { + /* + * For statistics only + */ + if (*status & UART_LSR_BI) { + *status &= ~(UART_LSR_FE | UART_LSR_PE); + up->port.icount.brk++; + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ + if (uart_handle_break(&up->port)) + goto ignore_char; + } else if (*status & UART_LSR_PE) + up->port.icount.parity++; + else if (*status & UART_LSR_FE) + up->port.icount.frame++; + if (*status & UART_LSR_OE) + up->port.icount.overrun++; + + /* + * Mask off conditions which should be ingored. + */ + *status &= up->port.read_status_mask; + +#ifdef CONFIG_SERIAL_M32R_PLDSIO_CONSOLE + if (up->port.line == up->port.cons->index) { + /* Recover the break flag from console xmit */ + *status |= up->lsr_break_flag; + up->lsr_break_flag = 0; + } +#endif + if (*status & UART_LSR_BI) { + DEBUG_INTR("handling break...."); + *tty->flip.flag_buf_ptr = TTY_BREAK; + } else if (*status & UART_LSR_PE) + *tty->flip.flag_buf_ptr = TTY_PARITY; + else if (*status & UART_LSR_FE) + *tty->flip.flag_buf_ptr = TTY_FRAME; + } + if (uart_handle_sysrq_char(&up->port, ch, regs)) + goto ignore_char; + if ((*status & up->port.ignore_status_mask) == 0) { + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } + if ((*status & UART_LSR_OE) && + tty->flip.count < TTY_FLIPBUF_SIZE) { + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character. + */ + *tty->flip.flag_buf_ptr = TTY_OVERRUN; + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } + ignore_char: + *status = serial_inp(up, (unsigned long)UART_LSR); + } while ((*status & UART_LSR_DR) && (max_count-- > 0)); + tty_flip_buffer_push(tty); +} + +static _INLINE_ void transmit_chars(struct uart_pldsio_port *up) +{ + struct circ_buf *xmit = &up->port.info->xmit; + int count; + + if (up->port.x_char) { + // XXXXXX serial_outp(up, UART_TX, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { + serialpldsio_stop_tx(&up->port, 0); + return; + } + + count = up->port.fifosize; + do { + serial_out(up, (unsigned long)UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + while (!serial_inp(up,(unsigned long) UART_LSR) & UART_LSR_THRE); + + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + DEBUG_INTR("THRE..."); + + if (uart_circ_empty(xmit)) + serialpldsio_stop_tx(&up->port, 0); +} + +/* + * This handles the interrupt from one port. + */ +static __inline__ void serialpldsio_handle_port(struct uart_pldsio_port *up, + unsigned int status, struct pt_regs *regs) +{ + DEBUG_INTR("status = %x...", status); + + if (status & 0x04) + receive_chars(up, &status, regs); + // check_modem_status(up); + if (status & 0x01) + transmit_chars(up); +} + +/* + * This is the serial driver's interrupt routine. + * + * Arjan thinks the old way was overly complex, so it got simplified. + * Alan disagrees, saying that need the complexity to handle the weird + * nature of ISA shared interrupts. (This is a special exception.) + * + * In order to handle ISA shared interrupts properly, we need to check + * that all ports have been serviced, and therefore the ISA interrupt + * line has been de-asserted. + * + * This means we need to loop through all ports. checking that they + * don't have an interrupt pending. + */ +static irqreturn_t serialpldsio_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + struct irq_info *i = dev_id; + struct list_head *l, *end = NULL; + int pass_counter = 0; + + DEBUG_INTR("serialpldsio_interrupt(%d)...", irq); + +#if 0 + if (irq == PLD_IRQ_SIO0_SND) + irq = PLD_IRQ_SIO0_RCV; +#endif + + spin_lock(&i->lock); + + l = i->head; + do { + struct uart_pldsio_port *up; + unsigned int sts; + + up = list_entry(l, struct uart_pldsio_port, list); + + sts = pldsio_in(up, SIOSTS); + if (sts & 0x5) { + spin_lock(&up->port.lock); + serialpldsio_handle_port(up, sts, regs); + spin_unlock(&up->port.lock); + + end = NULL; + } else if (end == NULL) + end = l; + + l = l->next; + + if (l == i->head && pass_counter++ > PASS_LIMIT) { + if (sts & 0xe0) + pldsio_error(&sts); + break; + } + } while (l != end); + + spin_unlock(&i->lock); + + DEBUG_INTR("end.\n"); + + return IRQ_HANDLED; +} + +/* + * To support ISA shared interrupts, we need to have one interrupt + * handler that ensures that the IRQ line has been deasserted + * before returning. Failing to do this will result in the IRQ + * line being stuck active, and, since ISA irqs are edge triggered, + * no more IRQs will be seen. + */ +static void serial_do_unlink(struct irq_info *i, struct uart_pldsio_port *up) +{ + spin_lock_irq(&i->lock); + + if (!list_empty(i->head)) { + if (i->head == &up->list) + i->head = i->head->next; + list_del(&up->list); + } else { + BUG_ON(i->head != &up->list); + i->head = NULL; + } + + spin_unlock_irq(&i->lock); +} + +static int serial_link_irq_chain(struct uart_pldsio_port *up) +{ + struct irq_info *i = irq_lists + up->port.irq; + int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0; + + spin_lock_irq(&i->lock); + + if (i->head) { + list_add(&up->list, i->head); + spin_unlock_irq(&i->lock); + + ret = 0; + } else { + INIT_LIST_HEAD(&up->list); + i->head = &up->list; + spin_unlock_irq(&i->lock); + + ret = request_irq(up->port.irq, serialpldsio_interrupt, + irq_flags, "PLDSIO0-RX", i); + ret |= request_irq(up->port.irq + 1, serialpldsio_interrupt, + irq_flags, "PLDSIO0-TX", i); + if (ret < 0) + serial_do_unlink(i, up); + } + + return ret; +} + +static void serial_unlink_irq_chain(struct uart_pldsio_port *up) +{ + struct irq_info *i = irq_lists + up->port.irq; + + BUG_ON(i->head == NULL); + + if (list_empty(i->head)) { + free_irq(up->port.irq, i); + free_irq(up->port.irq + 1, i); + } + + serial_do_unlink(i, up); +} + +/* + * This function is used to handle ports that do not have an + * interrupt. This doesn't work very well for 16450's, but gives + * barely passable results for a 16550A. (Although at the expense + * of much CPU overhead). + */ +static void serialpldsio_timeout(unsigned long data) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)data; + unsigned int timeout; + unsigned int sts; + + sts = pldsio_in(up, SIOSTS); + if (sts & 0x5) { + spin_lock(&up->port.lock); + serialpldsio_handle_port(up, sts, NULL); + spin_unlock(&up->port.lock); + } + + timeout = up->port.timeout; + timeout = timeout > 6 ? (timeout / 2 - 2) : 1; + mod_timer(&up->timer, jiffies + timeout); +} + +static unsigned int serialpldsio_tx_empty(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + unsigned long flags; + unsigned int ret; + + spin_lock_irqsave(&up->port.lock, flags); + ret = serial_in(up, (unsigned long)UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; + spin_unlock_irqrestore(&up->port.lock, flags); + + return ret; +} + +static unsigned int serialpldsio_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static void serialpldsio_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + +} + +static void serialpldsio_break_ctl(struct uart_port *port, int break_state) +{ + +} + +static int serialpldsio_startup(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + int retval; + + pldsio_init(); + + /* + * If the "interrupt" for this port doesn't correspond with any + * hardware interrupt, we use a timer-based system. The original + * driver used to do this with IRQ0. + */ + if (!is_real_interrupt(up->port.irq)) { + unsigned int timeout = up->port.timeout; + + timeout = timeout > 6 ? (timeout / 2 - 2) : 1; + + up->timer.data = (unsigned long)up; + mod_timer(&up->timer, jiffies + timeout); + } else { + retval = serial_link_irq_chain(up); + if (retval) + return retval; + } + + /* + * Finally, enable interrupts. Note: Modem status interrupts + * are set via set_termios(), which will be occurring imminently + * anyway, so we don't enable them here. + */ + up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; /* 0x04 */ + pldsio_out(up, SIOTRCR, up->ier); + + /* + * And clear the interrupt registers again for luck. + */ + pldsio_reset(); + + return 0; +} + +static void serialpldsio_shutdown(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + + /* + * Disable interrupts from this port + */ + up->ier = 0; + pldsio_out(up, SIOTRCR, 0); + + /* + * Disable break condition and FIFOs + */ + + pldsio_init(); + + if (!is_real_interrupt(up->port.irq)) + del_timer_sync(&up->timer); + else + serial_unlink_irq_chain(up); +} + +static unsigned int serialpldsio_get_divisor(struct uart_port *port, + unsigned int baud) +{ + return uart_get_divisor(port, baud); +} + +static void serialpldsio_set_termios(struct uart_port *port, + struct termios *termios, struct termios *old) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + unsigned char cval = 0; + unsigned long flags; + unsigned int baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + cval = 0x00; + break; + case CS6: + cval = 0x01; + break; + case CS7: + cval = 0x02; + break; + default: + case CS8: + cval = 0x03; + break; + } + + if (termios->c_cflag & CSTOPB) + cval |= 0x04; + if (termios->c_cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(termios->c_cflag & PARODD)) + cval |= UART_LCR_EPAR; +#ifdef CMSPAR + if (termios->c_cflag & CMSPAR) + cval |= UART_LCR_SPAR; +#endif + + /* + * Ask the core to calculate the divisor for us. + * (boot_cpu_data.bus_clock / (BAUD_RATE * 4))-1 + */ + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4); + quot = serialpldsio_get_divisor(port, baud); + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= UART_LSR_BI; + + /* + * Characteres to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_OE; + } + + /* + * ignore all characters if CREAD is not set + */ + if ((termios->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= UART_LSR_DR; + + /* + * CTS flow control flag and modem status interrupts + */ + up->ier &= ~UART_IER_MSI; + if (UART_ENABLE_MS(&up->port, termios->c_cflag)) + up->ier |= UART_IER_MSI; + + serial_out(up, (unsigned long)UART_IER, up->ier); + + up->lcr = cval; /* Save LCR */ + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static void serialpldsio_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + + if (up->pm) + up->pm(port, state, oldstate); +} + +/* + * Resource handling. This is complicated by the fact that resources + * depend on the port type. Maybe we should be claiming the standard + * 8250 ports, and then trying to get other resources as necessary? + */ +static int +serialpldsio_request_std_resource(struct uart_pldsio_port *up, struct resource **res) +{ + unsigned int size = 8 << up->port.regshift; + int ret = 0; + + switch (up->port.iotype) { + case SERIAL_IO_MEM: + if (up->port.mapbase) { + *res = request_mem_region(up->port.mapbase, size, "serial"); + if (!*res) + ret = -EBUSY; + } + break; + + case SERIAL_IO_HUB6: + case SERIAL_IO_PORT: + *res = request_region(up->port.iobase, size, "serial"); + if (!*res) + ret = -EBUSY; + break; + } + return ret; +} + +static int +serialpldsio_request_rsa_resource(struct uart_pldsio_port *up, struct resource **res) +{ + unsigned int size = 8 << up->port.regshift; + unsigned long start; + int ret = 0; + + switch (up->port.iotype) { + case SERIAL_IO_MEM: + if (up->port.mapbase) { + start = up->port.mapbase; + start += UART_RSA_BASE << up->port.regshift; + *res = request_mem_region(start, size, "serial-rsa"); + if (!*res) + ret = -EBUSY; + } + break; + + case SERIAL_IO_HUB6: + case SERIAL_IO_PORT: + start = up->port.iobase; + start += UART_RSA_BASE << up->port.regshift; + *res = request_region(up->port.iobase, size, "serial-rsa"); + if (!*res) + ret = -EBUSY; + break; + } + + return ret; +} + +static void serialpldsio_release_port(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + unsigned long start, offset = 0, size = 0; + + if (up->port.type == PORT_RSA) { + offset = UART_RSA_BASE << up->port.regshift; + size = 8; + } + + size <<= up->port.regshift; + + switch (up->port.iotype) { + case SERIAL_IO_MEM: + if (up->port.mapbase) { + /* + * Unmap the area. + */ + iounmap(up->port.membase); + up->port.membase = NULL; + + start = up->port.mapbase; + + if (size) + release_mem_region(start + offset, size); + release_mem_region(start, 8 << up->port.regshift); + } + break; + + case SERIAL_IO_HUB6: + case SERIAL_IO_PORT: + start = up->port.iobase; + + if (size) + release_region(start + offset, size); + release_region(start + offset, 8 << up->port.regshift); + break; + + default: + break; + } +} + +static int serialpldsio_request_port(struct uart_port *port) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + struct resource *res = NULL, *res_rsa = NULL; + int ret = 0; + + if (up->port.type == PORT_RSA){ + ret = serialpldsio_request_rsa_resource(up, &res_rsa); + if (ret < 0) + return ret; + } + ret = serialpldsio_request_std_resource(up, &res); + + /* + * If we have a mapbase, then request that as well. + */ + if (ret == 0 && up->port.flags & UPF_IOREMAP) { + int size = res->end - res->start + 1; + + up->port.membase = ioremap(up->port.mapbase, size); + if (!up->port.membase) + ret = -ENOMEM; + } + + if (ret < 0) { + if (res_rsa) + release_resource(res_rsa); + if (res) + release_resource(res); + } + return ret; +} + +static void serialpldsio_config_port(struct uart_port *port, int flags) +{ + struct uart_pldsio_port *up = (struct uart_pldsio_port *)port; + + spin_lock_irqsave(&up->port.lock, flags); + + up->port.type = PORT_SIO; + up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; + + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int +serialpldsio_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + if (ser->irq >= NR_IRQS || ser->irq < 0 || + ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || + ser->type > PORT_MAX_SIO || ser->type == PORT_CIRRUS || + ser->type == PORT_STARTECH) + return -EINVAL; + return 0; +} + +static const char * +serialpldsio_type(struct uart_port *port) +{ + int type = port->type; + + if (type >= ARRAY_SIZE(uart_config)) + type = 0; + return uart_config[type].name; +} + +static struct uart_ops serialpldsio_pops = { + .tx_empty = serialpldsio_tx_empty, + .set_mctrl = serialpldsio_set_mctrl, + .get_mctrl = serialpldsio_get_mctrl, + .stop_tx = serialpldsio_stop_tx, + .start_tx = serialpldsio_start_tx, + .stop_rx = serialpldsio_stop_rx, + .enable_ms = serialpldsio_enable_ms, + .break_ctl = serialpldsio_break_ctl, + .startup = serialpldsio_startup, + .shutdown = serialpldsio_shutdown, + .set_termios = serialpldsio_set_termios, + .pm = serialpldsio_pm, + .type = serialpldsio_type, + .release_port = serialpldsio_release_port, + .request_port = serialpldsio_request_port, + .config_port = serialpldsio_config_port, + .verify_port = serialpldsio_verify_port, +}; + +static struct uart_pldsio_port serialpldsio_ports[UART_NR]; + +static void __init serialpldsio_isa_init_ports(void) +{ + struct uart_pldsio_port *up; + static int first = 1; + int i; + + if (!first) + return; + first = 0; + + for (i = 0, up = serialpldsio_ports; i < ARRAY_SIZE(old_serial_port); + i++, up++) { + up->port.iobase = old_serial_port[i].port; + up->port.irq = irq_canonicalize(old_serial_port[i].irq); + up->port.uartclk = old_serial_port[i].baud_base * 16; + up->port.flags = old_serial_port[i].flags; + up->port.hub6 = old_serial_port[i].hub6; + up->port.membase = old_serial_port[i].iomem_base; + up->port.iotype = old_serial_port[i].io_type; + up->port.regshift = old_serial_port[i].iomem_reg_shift; + up->port.ops = &serialpldsio_pops; + if (share_irqs_pldsio) + up->port.flags |= UPF_SHARE_IRQ; + } +} + +static void __init serialpldsio_register_ports(struct uart_driver *drv) +{ + int i; + + serialpldsio_isa_init_ports(); + + for (i = 0; i < UART_NR; i++) { + struct uart_pldsio_port *up = &serialpldsio_ports[i]; + + up->port.line = i; + up->port.ops = &serialpldsio_pops; + init_timer(&up->timer); + up->timer.function = serialpldsio_timeout; + + /* + * ALPHA_KLUDGE_MCR needs to be killed. + */ + up->mcr_mask = ~ALPHA_KLUDGE_MCR; + up->mcr_force = ALPHA_KLUDGE_MCR; + + uart_add_one_port(drv, &up->port); + } +} + +#ifdef CONFIG_SERIAL_M32R_PLDSIO_CONSOLE + +/* + * Wait for transmitter & holding register to empty + */ +static __inline__ void wait_for_xmitr(struct uart_pldsio_port *up) +{ + unsigned int status, tmout = 10000; + + /* Wait up to 10ms for the character(s) to be sent. */ + do { + status = pldsio_in(up, SIOSTS); + + if (--tmout == 0) + break; + udelay(1); + } while ((status & UART_EMPTY) != UART_EMPTY); + + /* Wait up to 1s for flow control if necessary */ + if (up->port.flags & UPF_CONS_FLOW) { + tmout = 1000000; + while (--tmout) + udelay(1); + } +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console_lock must be held when we get here. + */ +static void serialpldsio_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_pldsio_port *up = &serialpldsio_ports[co->index]; + unsigned int ier; + int i; + + /* + * First save the UER then disable the interrupts + */ + ier = pldsio_in(up, SIOTRCR); + pldsio_out(up, SIOTRCR, 0); + + /* + * Now, do each character + */ + for (i = 0; i < count; i++, s++) { + wait_for_xmitr(up); + + /* + * Send the character out. + * If a LF, also do CR... + */ + pldsio_out(up, SIOTXB, *s); + + if (*s == 10) { + wait_for_xmitr(up); + pldsio_out(up, SIOTXB, 13); + } + } + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up); + pldsio_out(up, SIOTRCR, ier); +} + +static int __init serialpldsio_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index >= UART_NR) + co->index = 0; + port = &serialpldsio_ports[co->index].port; + + /* + * Temporary fix. + */ + spin_lock_init(&port->lock); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +extern struct uart_driver serialpldsio_reg; +static struct console serialpldsio_console = { + .name = "ttyD", + .write = serialpldsio_console_write, + .device = uart_console_device, + .setup = serialpldsio_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &serialpldsio_reg, +}; + +static int __init serialpldsio_console_init(void) +{ + pldsio_reset(); + pldsio_init(); + serialpldsio_isa_init_ports(); + register_console(&serialpldsio_console); + return 0; +} +console_initcall(serialpldsio_console_init); + +#define SERIALPLDSIO_CONSOLE &serialpldsio_console +#else +#define SERIALPLDSIO_CONSOLE NULL +#endif + +static struct uart_driver serialpldsio_reg = { + .owner = THIS_MODULE, + .driver_name = "pldsio", + .devfs_name = "tts/", + .dev_name = "ttyD", + .major = TTY_MAJOR, + .minor = 80, + .nr = UART_NR, + .cons = SERIALPLDSIO_CONSOLE, +}; + +/* + * register_serial and unregister_serial allows for 16x50 serial ports to be + * configured at run-time, to support PCMCIA modems. + */ + +static int __register_serialpldsio(struct serial_struct *req, int line) +{ + struct uart_port port; + + port.iobase = req->port; + port.membase = req->iomem_base; + port.irq = req->irq; + port.uartclk = req->baud_base * 16; + port.fifosize = req->xmit_fifo_size; + port.regshift = req->iomem_reg_shift; + port.iotype = req->io_type; + port.flags = req->flags | UPF_BOOT_AUTOCONF; + port.mapbase = req->iomap_base; + port.line = line; + + if (share_irqs_pldsio) + port.flags |= UPF_SHARE_IRQ; + + if (HIGH_BITS_OFFSET) + port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET; + + /* + * If a clock rate wasn't specified by the low level + * driver, then default to the standard clock rate. + */ + if (port.uartclk == 0) + port.uartclk = BASE_BAUD * 16; + + return uart_register_port(&serialpldsio_reg, &port); +} + +/** + * register_serial - configure a 16x50 serial port at runtime + * @req: request structure + * + * Configure the serial port specified by the request. If the + * port exists and is in use an error is returned. If the port + * is not currently in the table it is added. + * + * The port is then probed and if necessary the IRQ is autodetected + * If this fails an error is returned. + * + * On success the port is ready to use and the line number is returned. + */ +int register_serialpldsio(struct serial_struct *req) +{ + return __register_serialpldsio(req, -1); +} + +int __init early_serialpldsio_setup(struct uart_port *port) +{ + serialpldsio_isa_init_ports(); + serialpldsio_ports[port->line].port = *port; + serialpldsio_ports[port->line].port.ops = &serialpldsio_pops; + + return 0; +} + +/** + * unregister_serial - remove a 16x50 serial port at runtime + * @line: serial line number + * + * Remove one serial port. This may be called from interrupt + * context. + */ +void unregister_serialpldsio(int line) +{ + uart_unregister_port(&serialpldsio_reg, line); +} + +/* + * This is for ISAPNP only. + */ +void serialpldsio_get_irq_map(unsigned int *map) +{ + int i; + + for (i = 0; i < UART_NR; i++) { + if (serialpldsio_ports[i].port.type != PORT_UNKNOWN && + serialpldsio_ports[i].port.irq < 16) + *map |= 1 << serialpldsio_ports[i].port.irq; + } +} + +/** + * serialpldsio_suspend_port - suspend one serial port + * @line: serial line number + * + * Suspend one serial port. + */ +void serialpldsio_suspend_port(int line) +{ + uart_suspend_port(&serialpldsio_reg, &serialpldsio_ports[line].port); +} + +/** + * serialpldsio_resume_port - resume one serial port + * @line: serial line number + * + * Resume one serial port. + */ +void serialpldsio_resume_port(int line) +{ + uart_resume_port(&serialpldsio_reg, &serialpldsio_ports[line].port); +} + +static int __init serialpldsio_init(void) +{ + int ret, i; + + printk(KERN_INFO "Serial: M32R PLDSIO driver $Revision: 1.2 $ " + "IRQ sharing %sabled\n", share_irqs_pldsio ? "en" : "dis"); + + for (i = 0; i < NR_IRQS; i++) + spin_lock_init(&irq_lists[i].lock); + + ret = uart_register_driver(&serialpldsio_reg); + if (ret >= 0) + serialpldsio_register_ports(&serialpldsio_reg); + + return ret; +} + +static void __exit serialpldsio_exit(void) +{ + int i; + + for (i = 0; i < UART_NR; i++) + uart_remove_one_port(&serialpldsio_reg, &serialpldsio_ports[i].port); + + uart_unregister_driver(&serialpldsio_reg); +} + +module_init(serialpldsio_init); +module_exit(serialpldsio_exit); + +EXPORT_SYMBOL(register_serialpldsio); +EXPORT_SYMBOL(unregister_serialpldsio); +EXPORT_SYMBOL(serialpldsio_get_irq_map); +EXPORT_SYMBOL(serialpldsio_suspend_port); +EXPORT_SYMBOL(serialpldsio_resume_port); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Generic M32R PLDSIO serial driver $Revision: 1.2 $"); + +MODULE_PARM(share_irqs_pldsio, "i"); +MODULE_PARM_DESC(share_irqs_pldsio, "Share IRQs with other non-M32R PLDSIO devices" + " (unsafe)"); + diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/m32r-pld_sio.h linux-2.6.8.1/drivers/serial/m32r-pld_sio.h --- linux-2.6.8.1.org/drivers/serial/m32r-pld_sio.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/m32r-pld_sio.h 2004-04-05 11:33:47.000000000 +0900 @@ -0,0 +1,59 @@ +/* + * linux/drivers/char/8250.h + * + * Driver for 8250/16550-type serial ports + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright (C) 2001 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * $Id: m32r-pld_sio.h,v 1.1.1.1 2004/03/25 04:29:01 hitoshiy Exp $ + */ + +#include + +struct serialpldsio_probe { + struct module *owner; + int (*pci_init_one)(struct pci_dev *dev); + void (*pci_remove_one)(struct pci_dev *dev); + void (*pnp_init)(void); +}; + +int serialpldsio_register_probe(struct serialpldsio_probe *probe); +void serialpldsio_unregister_probe(struct serialpldsio_probe *probe); +void serialpldsio_get_irq_map(unsigned int *map); +void serialpldsio_suspend_port(int line); +void serialpldsio_resume_port(int line); + +struct old_serial_port { + unsigned int uart; + unsigned int baud_base; + unsigned int port; + unsigned int irq; + unsigned int flags; + unsigned char hub6; + unsigned char io_type; + unsigned char *iomem_base; + unsigned short iomem_reg_shift; +}; + +#undef SERIAL_DEBUG_PCI + +// #define _INLINE_ __inline__ +#define _INLINE_ + +#define PROBE_RSA (1 << 0) +#define PROBE_ANY (~0) + +#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) + +#ifdef CONFIG_SERIAL_PLDSIO_SHARE_IRQ +#define SERIALPLDSIO_SHARE_IRQS 1 +#else +#define SERIALPLDSIO_SHARE_IRQS 0 +#endif diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/m32r-pld_sio_reg.h linux-2.6.8.1/drivers/serial/m32r-pld_sio_reg.h --- linux-2.6.8.1.org/drivers/serial/m32r-pld_sio_reg.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/m32r-pld_sio_reg.h 2004-03-25 13:29:01.000000000 +0900 @@ -0,0 +1,295 @@ +/* + * include/linux/serial_reg.h + * + * Copyright (C) 1992, 1994 by Theodore Ts'o. + * + * Redistribution of this file is permitted under the terms of the GNU + * Public License (GPL) + * + * These are the UART port assignments, expressed as offsets from the base + * register. These assignments should hold for any serial port based on + * a 8250, 16450, or 16550(A). + */ + +#ifndef _PLDSIO_REG_H +#define _PLDSIO_REG_H + +#define SIOCR 0x000 +#define SIOMOD0 0x002 +#define SIOMOD1 0x004 +#define SIOSTS 0x006 +#define SIOTRCR 0x008 +#define SIOBAUR 0x00a +// #define SIORBAUR 0x018 +#define SIOTXB 0x00c +#define SIORXB 0x00e + +#define UART_RX PLD_ESIO0RXB /* In: Receive buffer (DLAB=0) */ +#define UART_TX PLD_ESIO0TXB /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels + * XR16C85x only */ + +#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER PLD_ESIO0INTCR /* Out: Interrupt Enable Register */ +#define UART_FCTR 0 /* (LCR=BF) Feature Control Register + * XR16C85x only */ + +#define UART_IIR 0 /* In: Interrupt ID Register */ +#define UART_FCR 0 /* Out: FIFO Control Register */ +#define UART_EFR 0 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ + +#define UART_LCR 0 /* Out: Line Control Register */ +#define UART_MCR 0 /* Out: Modem Control Register */ +#define UART_LSR PLD_ESIO0STS /* In: Line Status Register */ +#define UART_MSR 0 /* In: Modem Status Register */ +#define UART_SCR 0 /* I/O: Scratch Register */ +#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register + * FCTR bit 6 selects SCR or EMSR + * XR16c85x only */ + +#define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 redefinitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ +/* TI 16750 definitions */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x02 /* Transmitter empty */ +#define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x00 /* Break interrupt indicator */ +#define UART_LSR_FE 0x00 /* Frame error indicator */ +#define UART_LSR_PE 0x00 /* Parity error indicator */ +#define UART_LSR_OE 0x00 /* Overrun error indicator */ +#define UART_LSR_DR 0x04 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x00 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x04 /* Enable receiver data interrupt */ +/* + * Sleep mode for ST16650 and TI16750. + * Note that for 16650, EFR-bit 4 must be selected as well. + */ +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +//#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_RTS SIO_SIO0MOD0_RTSS /* RTS complement */ +//#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +/* + * These are the definitions for the Extended Features Register + * (StarTech 16C660 only, when DLAB=1) + */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ECB 0x10 /* Enhanced control bit */ +/* + * the low four bits control software flow control + */ + +/* + * These register definitions are for the 16C950 + */ +#define UART_ASR 0x01 /* Additional Status Register */ +#define UART_RFL 0x03 /* Receiver FIFO level */ +#define UART_TFL 0x04 /* Transmitter FIFO level */ +#define UART_ICR 0x05 /* Index Control Register */ + +/* The 16950 ICR registers */ +#define UART_ACR 0x00 /* Additional Control Register */ +#define UART_CPR 0x01 /* Clock Prescalar Register */ +#define UART_TCR 0x02 /* Times Clock Register */ +#define UART_CKS 0x03 /* Clock Select Register */ +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ +#define UART_FCL 0x06 /* Flow Control Level Lower */ +#define UART_FCH 0x07 /* Flow Control Level Higher */ +#define UART_ID1 0x08 /* ID #1 */ +#define UART_ID2 0x09 /* ID #2 */ +#define UART_ID3 0x0A /* ID #3 */ +#define UART_REV 0x0B /* Revision */ +#define UART_CSR 0x0C /* Channel Software Reset */ +#define UART_NMR 0x0D /* Nine-bit Mode Register */ +#define UART_CTR 0xFF + +/* + * The 16C950 Additional Control Reigster + */ +#define UART_ACR_RXDIS 0x01 /* Receiver disable */ +#define UART_ACR_TXDIS 0x02 /* Receiver disable */ +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */ +#define UART_ACR_ASREN 0x80 /* Additional status enable */ + +/* + * These are the definitions for the Feature Control Register + * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable + * Register, UART register #1) + */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ + +/* + * These are the definitions for the Enhanced Mode Select Register + * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the + * Scratch register, UART register #7) + */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ + +/* + * These are the definitions for the Programmable Trigger + * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX + * register, UART register #0) + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 + +/* + * These definitions are for the RSA-DV II/S card, from + * + * Kiyokazu SUTO + */ + +#define UART_RSA_BASE (-8) + +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ + +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ + +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ + +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ + +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ + +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ + +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ + +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ + +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ + +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ + +/* + * The RSA DSV/II board has two fixed clock frequencies. One is the + * standard rate, and the other is 8 times faster. + */ +#define SERIAL_RSA_BAUD_BASE (921600) +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) + +#endif /* _PLDSIO_REG_H */ + diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/m32r_sio.c linux-2.6.8.1/drivers/serial/m32r_sio.c --- linux-2.6.8.1.org/drivers/serial/m32r_sio.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/m32r_sio.c 2004-08-30 10:24:02.000000000 +0900 @@ -0,0 +1,1290 @@ +/* + * linux/drivers/char/8250.c + * + * Driver for 8250/16550-type serial ports + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright (C) 2001 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * $Id: m32r_sio.c,v 1.4 2004/03/31 10:25:29 takata Exp $ + * + * A note about mapbase / membase + * + * mapbase is the physical address of the IO port. Currently, we don't + * support this very well, and it may well be dropped from this driver + * in future. As such, mapbase should be NULL. + * + * membase is an 'ioremapped' cookie. This is compatible with the old + * serial.c driver, and is currently the preferred form. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#define PORT_SIO 1 +#define PORT_MAX_SIO 1 +#define BAUD_RATE 115200 + +#include +#include "m32r_sio.h" +#include "m32r_sio_reg.h" + +/* + * Configuration: + * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option + * is unsafe when used on edge-triggered interrupts. + */ +unsigned int share_irqs_sio = SERIALSIO_SHARE_IRQS; + +/* + * Debugging. + */ +#if 0 +#define DEBUG_AUTOCONF(fmt...) printk(fmt) +#else +#define DEBUG_AUTOCONF(fmt...) do { } while (0) +#endif + +#if 0 +#define DEBUG_INTR(fmt...) printk(fmt) +#else +#define DEBUG_INTR(fmt...) do { } while (0) +#endif + +#define PASS_LIMIT 256 + +/* + * We default to IRQ0 for the "no irq" hack. Some + * machine types want others as well - they're free + * to redefine this in their header file. + */ +#define is_real_interrupt(irq) ((irq) != 0) + +/* + * This converts from our new CONFIG_ symbols to the symbols + * that asm/serial.h expects. You _NEED_ to comment out the + * linux/config.h include contained inside asm/serial.h for + * this to work. + */ +#undef CONFIG_SERIAL_MANY_PORTS +#undef CONFIG_SERIAL_DETECT_IRQ +#undef CONFIG_SERIAL_MULTIPORT +#undef CONFIG_HUB6 + +#ifdef CONFIG_SERIAL_SIO_DETECT_IRQ +#define CONFIG_SERIAL_DETECT_IRQ 1 +#endif +#ifdef CONFIG_SERIAL_SIO_MULTIPORT +#define CONFIG_SERIAL_MULTIPORT 1 +#endif +#ifdef CONFIG_SERIAL_SIO_MANY_PORTS +#define CONFIG_SERIAL_MANY_PORTS 1 +#endif + +/* + * HUB6 is always on. This will be removed once the header + * files have been cleaned. + */ +#define CONFIG_HUB6 1 + +#include + +static struct old_serial_port old_serial_port[] = { + { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, STD_COM_FLAGS } +}; + +#define UART_NR ARRAY_SIZE(old_serial_port) + +struct uart_sio_port { + struct uart_port port; + struct timer_list timer; /* "no irq" timer */ + struct list_head list; /* ports on this IRQ */ + unsigned short rev; + unsigned char acr; + unsigned char ier; + unsigned char lcr; + unsigned char mcr_mask; /* mask of user bits */ + unsigned char mcr_force; /* mask of forced bits */ + unsigned char lsr_break_flag; + + /* + * We provide a per-port pm hook. + */ + void (*pm)(struct uart_port *port, + unsigned int state, unsigned int old); +}; + +struct irq_info { + spinlock_t lock; + struct list_head *head; +}; + +static struct irq_info irq_lists[NR_IRQS]; + +/* + * Here we define the default xmit fifo size used for each type of UART. + */ +static const struct serial_uart_config uart_config[PORT_MAX_SIO+1] = { + { "unknown", 1, 0 }, + { "M32RSIO", 1, 0 } +}; + +static void sio_reset(void) +{ + int i, j; + + outl(0x00000300, M32R_SIO0_CR_PORTL); /* init status */ + outl(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */ + outl(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */ + + i = boot_cpu_data.bus_clock / (BAUD_RATE * 16); + j = (boot_cpu_data.bus_clock - (i * BAUD_RATE * 16)) / BAUD_RATE; + i -= 1; + j = (j + 1) >> 1; + + outl(i, M32R_SIO0_BAUR_PORTL); + outl(j, M32R_SIO0_RBAUR_PORTL); + outl(0x00000000, M32R_SIO0_TRCR_PORTL); + outl(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */ +} + +static void sio_init(void) +{ + unsigned int tmp; + + tmp = inl(M32R_SIO0_RXB_PORTL); + tmp = inl(M32R_SIO0_RXB_PORTL); + tmp = inl(M32R_SIO0_STS_PORTL); + outl(0x00000003, M32R_SIO0_CR_PORTL); +} + +static void sio_error(int *status) +{ + printk("SIO0 error[%04x]\n", *status); + do { + sio_init(); + } while ((*status = inl(M32R_SIO0_CR_PORTL)) != 3); +} + +static _INLINE_ unsigned int sio_in(struct uart_sio_port *up, int offset) +{ + return inl(up->port.iobase + offset); +} + +static _INLINE_ void sio_out(struct uart_sio_port *up, int offset, int value) +{ + outl(value, up->port.iobase + offset); +} + +static _INLINE_ unsigned int serial_in(struct uart_sio_port *up, int offset) +{ + if (!offset) + return 0; + + return inl(offset); +} + +static _INLINE_ void +serial_out(struct uart_sio_port *up, int offset, int value) +{ + if (!offset) + return; + + outl(value, offset); +} + +/* + * We used to support using pause I/O for certain machines. We + * haven't supported this for a while, but just in case it's badly + * needed for certain old 386 machines, I've left these #define's + * in.... + */ +#define serial_inp(up, offset) serial_in(up, offset) +#define serial_outp(up, offset, value) serial_out(up, offset, value) + +static void serialsio_stop_tx(struct uart_port *port, unsigned int tty_stop) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + if (up->ier & UART_IER_THRI) { + up->ier &= ~UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serialsio_start_tx(struct uart_port *port, unsigned int tty_start) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + if (!(up->ier & UART_IER_THRI)) { + up->ier |= UART_IER_THRI; + serial_out(up, UART_IER, up->ier); + } +} + +static void serialsio_stop_rx(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + up->ier &= ~UART_IER_RLSI; + up->port.read_status_mask &= ~UART_LSR_DR; + serial_out(up, UART_IER, up->ier); +} + +static void serialsio_enable_ms(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + up->ier |= UART_IER_MSI; + serial_out(up, UART_IER, up->ier); +} + +static _INLINE_ void receive_chars(struct uart_sio_port *up, int *status, + struct pt_regs *regs) +{ + struct tty_struct *tty = up->port.info->tty; + unsigned char ch; + int max_count = 256; + + do { + if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { + tty->flip.work.func((void *)tty); + if (tty->flip.count >= TTY_FLIPBUF_SIZE) + return; // if TTY_DONT_FLIP is set + } + ch = sio_in(up, SIORXB); + *tty->flip.char_buf_ptr = ch; + *tty->flip.flag_buf_ptr = TTY_NORMAL; + up->port.icount.rx++; + + if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | + UART_LSR_FE | UART_LSR_OE))) { + /* + * For statistics only + */ + if (*status & UART_LSR_BI) { + *status &= ~(UART_LSR_FE | UART_LSR_PE); + up->port.icount.brk++; + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ + if (uart_handle_break(&up->port)) + goto ignore_char; + } else if (*status & UART_LSR_PE) + up->port.icount.parity++; + else if (*status & UART_LSR_FE) + up->port.icount.frame++; + if (*status & UART_LSR_OE) + up->port.icount.overrun++; + + /* + * Mask off conditions which should be ingored. + */ + *status &= up->port.read_status_mask; + +#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE + if (up->port.line == up->port.cons->index) { + /* Recover the break flag from console xmit */ + *status |= up->lsr_break_flag; + up->lsr_break_flag = 0; + } +#endif + if (*status & UART_LSR_BI) { + DEBUG_INTR("handling break...."); + *tty->flip.flag_buf_ptr = TTY_BREAK; + } else if (*status & UART_LSR_PE) + *tty->flip.flag_buf_ptr = TTY_PARITY; + else if (*status & UART_LSR_FE) + *tty->flip.flag_buf_ptr = TTY_FRAME; + } + if (uart_handle_sysrq_char(&up->port, ch, regs)) + goto ignore_char; + if ((*status & up->port.ignore_status_mask) == 0) { + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } + if ((*status & UART_LSR_OE) && + tty->flip.count < TTY_FLIPBUF_SIZE) { + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character. + */ + *tty->flip.flag_buf_ptr = TTY_OVERRUN; + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } + ignore_char: + *status = serial_inp(up, UART_LSR); + } while ((*status & UART_LSR_DR) && (max_count-- > 0)); + tty_flip_buffer_push(tty); +} + +static _INLINE_ void transmit_chars(struct uart_sio_port *up) +{ + struct circ_buf *xmit = &up->port.info->xmit; + int count; + + if (up->port.x_char) { + serial_outp(up, UART_TX, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { + serialsio_stop_tx(&up->port, 0); + return; + } + + count = up->port.fifosize; + do { + serial_out(up, UART_TX, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + while (!serial_inp(up, UART_LSR) & UART_LSR_THRE); + + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + DEBUG_INTR("THRE..."); + + if (uart_circ_empty(xmit)) + serialsio_stop_tx(&up->port, 0); +} + +/* + * This handles the interrupt from one port. + */ +static __inline__ void serialsio_handle_port(struct uart_sio_port *up, + unsigned int status, struct pt_regs *regs) +{ + DEBUG_INTR("status = %x...", status); + + if (status & 0x04) + receive_chars(up, &status, regs); + // check_modem_status(up); + if (status & 0x01) + transmit_chars(up); +} + +/* + * This is the serial driver's interrupt routine. + * + * Arjan thinks the old way was overly complex, so it got simplified. + * Alan disagrees, saying that need the complexity to handle the weird + * nature of ISA shared interrupts. (This is a special exception.) + * + * In order to handle ISA shared interrupts properly, we need to check + * that all ports have been serviced, and therefore the ISA interrupt + * line has been de-asserted. + * + * This means we need to loop through all ports. checking that they + * don't have an interrupt pending. + */ +static irqreturn_t serialsio_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + struct irq_info *i = dev_id; + struct list_head *l, *end = NULL; + int pass_counter = 0; + + DEBUG_INTR("serialsio_interrupt(%d)...", irq); + + if (irq == M32R_IRQ_SIO0_S) + irq = M32R_IRQ_SIO0_R; + + spin_lock(&i->lock); + + l = i->head; + do { + struct uart_sio_port *up; + unsigned int sts; + + up = list_entry(l, struct uart_sio_port, list); + + sts = sio_in(up, SIOSTS); + if (sts & 0x5) { + spin_lock(&up->port.lock); + serialsio_handle_port(up, sts, regs); + spin_unlock(&up->port.lock); + + end = NULL; + } else if (end == NULL) + end = l; + + l = l->next; + + if (l == i->head && pass_counter++ > PASS_LIMIT) { + if (sts & 0xe0) + sio_error(&sts); + break; + } + } while (l != end); + + spin_unlock(&i->lock); + + DEBUG_INTR("end.\n"); + + return IRQ_HANDLED; +} + +/* + * To support ISA shared interrupts, we need to have one interrupt + * handler that ensures that the IRQ line has been deasserted + * before returning. Failing to do this will result in the IRQ + * line being stuck active, and, since ISA irqs are edge triggered, + * no more IRQs will be seen. + */ +static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up) +{ + spin_lock_irq(&i->lock); + + if (!list_empty(i->head)) { + if (i->head == &up->list) + i->head = i->head->next; + list_del(&up->list); + } else { + BUG_ON(i->head != &up->list); + i->head = NULL; + } + + spin_unlock_irq(&i->lock); +} + +static int serial_link_irq_chain(struct uart_sio_port *up) +{ + struct irq_info *i = irq_lists + up->port.irq; + int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0; + + spin_lock_irq(&i->lock); + + if (i->head) { + list_add(&up->list, i->head); + spin_unlock_irq(&i->lock); + + ret = 0; + } else { + INIT_LIST_HEAD(&up->list); + i->head = &up->list; + spin_unlock_irq(&i->lock); + + ret = request_irq(up->port.irq, serialsio_interrupt, + irq_flags, "SIO0-RX", i); + ret |= request_irq(up->port.irq + 1, serialsio_interrupt, + irq_flags, "SIO0-TX", i); + if (ret < 0) + serial_do_unlink(i, up); + } + + return ret; +} + +static void serial_unlink_irq_chain(struct uart_sio_port *up) +{ + struct irq_info *i = irq_lists + up->port.irq; + + BUG_ON(i->head == NULL); + + if (list_empty(i->head)) { + free_irq(up->port.irq, i); + free_irq(up->port.irq + 1, i); + } + + serial_do_unlink(i, up); +} + +/* + * This function is used to handle ports that do not have an + * interrupt. This doesn't work very well for 16450's, but gives + * barely passable results for a 16550A. (Although at the expense + * of much CPU overhead). + */ +static void serialsio_timeout(unsigned long data) +{ + struct uart_sio_port *up = (struct uart_sio_port *)data; + unsigned int timeout; + unsigned int sts; + + sts = sio_in(up, SIOSTS); + if (sts & 0x5) { + spin_lock(&up->port.lock); + serialsio_handle_port(up, sts, NULL); + spin_unlock(&up->port.lock); + } + + timeout = up->port.timeout; + timeout = timeout > 6 ? (timeout / 2 - 2) : 1; + mod_timer(&up->timer, jiffies + timeout); +} + +static unsigned int serialsio_tx_empty(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + unsigned long flags; + unsigned int ret; + + spin_lock_irqsave(&up->port.lock, flags); + ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; + spin_unlock_irqrestore(&up->port.lock, flags); + + return ret; +} + +static unsigned int serialsio_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static void serialsio_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + +} + +static void serialsio_break_ctl(struct uart_port *port, int break_state) +{ + +} + +static int serialsio_startup(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + int retval; + + sio_init(); + + /* + * If the "interrupt" for this port doesn't correspond with any + * hardware interrupt, we use a timer-based system. The original + * driver used to do this with IRQ0. + */ + if (!is_real_interrupt(up->port.irq)) { + unsigned int timeout = up->port.timeout; + + timeout = timeout > 6 ? (timeout / 2 - 2) : 1; + + up->timer.data = (unsigned long)up; + mod_timer(&up->timer, jiffies + timeout); + } else { + retval = serial_link_irq_chain(up); + if (retval) + return retval; + } + + /* + * Finally, enable interrupts. Note: Modem status interrupts + * are set via set_termios(), which will be occurring imminently + * anyway, so we don't enable them here. + */ + up->ier = 0x0c; + sio_out(up, SIOTRCR, up->ier); + + /* + * And clear the interrupt registers again for luck. + */ + sio_reset(); + + return 0; +} + +static void serialsio_shutdown(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + /* + * Disable interrupts from this port + */ + up->ier = 0; + sio_out(up, SIOTRCR, 0); + + /* + * Disable break condition and FIFOs + */ + + sio_init(); + + if (!is_real_interrupt(up->port.irq)) + del_timer_sync(&up->timer); + else + serial_unlink_irq_chain(up); +} + +static unsigned int serialsio_get_divisor(struct uart_port *port, + unsigned int baud) +{ + return uart_get_divisor(port, baud); +} + +static void serialsio_set_termios(struct uart_port *port, + struct termios *termios, struct termios *old) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + unsigned char cval = 0; + unsigned long flags; + unsigned int baud, quot, i, j; + + switch (termios->c_cflag & CSIZE) { + case CS5: + cval = 0x00; + break; + case CS6: + cval = 0x01; + break; + case CS7: + cval = 0x02; + break; + default: + case CS8: + cval = 0x03; + break; + } + + if (termios->c_cflag & CSTOPB) + cval |= 0x04; + if (termios->c_cflag & PARENB) + cval |= UART_LCR_PARITY; + if (!(termios->c_cflag & PARODD)) + cval |= UART_LCR_EPAR; +#ifdef CMSPAR + if (termios->c_cflag & CMSPAR) + cval |= UART_LCR_SPAR; +#endif + + /* + * Ask the core to calculate the divisor for us. + */ + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); + quot = serialsio_get_divisor(port, baud); + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + i = boot_cpu_data.bus_clock / (baud * 16); + j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud; + i -= 1; + j = (j + 1) >> 1; + + outl(i, M32R_SIO0_BAUR_PORTL); + outl(j, M32R_SIO0_RBAUR_PORTL); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; + if (termios->c_iflag & INPCK) + up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + up->port.read_status_mask |= UART_LSR_BI; + + /* + * Characteres to ignore + */ + up->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; + if (termios->c_iflag & IGNBRK) { + up->port.ignore_status_mask |= UART_LSR_BI; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + up->port.ignore_status_mask |= UART_LSR_OE; + } + + /* + * ignore all characters if CREAD is not set + */ + if ((termios->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= UART_LSR_DR; + + /* + * CTS flow control flag and modem status interrupts + */ + up->ier &= ~UART_IER_MSI; + if (UART_ENABLE_MS(&up->port, termios->c_cflag)) + up->ier |= UART_IER_MSI; + + serial_out(up, UART_IER, up->ier); + + up->lcr = cval; /* Save LCR */ + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static void serialsio_pm(struct uart_port *port, unsigned int state, + unsigned int oldstate) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + if (up->pm) + up->pm(port, state, oldstate); +} + +/* + * Resource handling. This is complicated by the fact that resources + * depend on the port type. Maybe we should be claiming the standard + * 8250 ports, and then trying to get other resources as necessary? + */ +static int +serialsio_request_std_resource(struct uart_sio_port *up, struct resource **res) +{ + unsigned int size = 8 << up->port.regshift; + int ret = 0; + + switch (up->port.iotype) { + case SERIAL_IO_MEM: + if (up->port.mapbase) { + *res = request_mem_region(up->port.mapbase, size, "serial"); + if (!*res) + ret = -EBUSY; + } + break; + + case SERIAL_IO_HUB6: + case SERIAL_IO_PORT: + *res = request_region(up->port.iobase, size, "serial"); + if (!*res) + ret = -EBUSY; + break; + } + return ret; +} + +static int +serialsio_request_rsa_resource(struct uart_sio_port *up, struct resource **res) +{ + unsigned int size = 8 << up->port.regshift; + unsigned long start; + int ret = 0; + + switch (up->port.iotype) { + case SERIAL_IO_MEM: + if (up->port.mapbase) { + start = up->port.mapbase; + start += UART_RSA_BASE << up->port.regshift; + *res = request_mem_region(up->port.mapbase, size, "serial-rsa"); + if (!*res) + ret = -EBUSY; + } + break; + + case SERIAL_IO_HUB6: + case SERIAL_IO_PORT: + start = up->port.iobase; + start += UART_RSA_BASE << up->port.regshift; + *res = request_region(up->port.iobase, size, "serial-rsa"); + if (!*res) + ret = -EBUSY; + break; + } + + return ret; +} + +static void serialsio_release_port(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + unsigned long start, offset = 0, size = 0; + + if (up->port.type == PORT_RSA) { + offset = UART_RSA_BASE << up->port.regshift; + size = 8; + } + + size <<= up->port.regshift; + + switch (up->port.iotype) { + case SERIAL_IO_MEM: + if (up->port.mapbase) { + /* + * Unmap the area. + */ + iounmap(up->port.membase); + up->port.membase = NULL; + + start = up->port.mapbase; + + if (size) + release_mem_region(start + offset, size); + release_mem_region(start, 8 << up->port.regshift); + } + break; + + case SERIAL_IO_HUB6: + case SERIAL_IO_PORT: + start = up->port.iobase; + + if (size) + release_region(start + offset, size); + release_region(start + offset, 8 << up->port.regshift); + break; + + default: + break; + } +} + +static int serialsio_request_port(struct uart_port *port) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + struct resource *res = NULL, *res_rsa = NULL; + int ret = 0; + + if (up->port.type == PORT_RSA){ + ret = serialsio_request_rsa_resource(up, &res_rsa); + if (ret < 0) + return ret; + } + ret = serialsio_request_std_resource(up, &res); + + /* + * If we have a mapbase, then request that as well. + */ + if (ret == 0 && up->port.flags & UPF_IOREMAP) { + int size = res->end - res->start + 1; + + up->port.membase = ioremap(up->port.mapbase, size); + if (!up->port.membase) + ret = -ENOMEM; + } + + if (ret < 0) { + if (res_rsa) + release_resource(res_rsa); + if (res) + release_resource(res); + } + return ret; +} + +static void serialsio_config_port(struct uart_port *port, int flags) +{ + struct uart_sio_port *up = (struct uart_sio_port *)port; + + spin_lock_irqsave(&up->port.lock, flags); + + up->port.type = PORT_SIO; + up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; + + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static int +serialsio_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + if (ser->irq >= NR_IRQS || ser->irq < 0 || + ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || + ser->type > PORT_MAX_SIO || ser->type == PORT_CIRRUS || + ser->type == PORT_STARTECH) + return -EINVAL; + return 0; +} + +static const char * +serialsio_type(struct uart_port *port) +{ + int type = port->type; + + if (type >= ARRAY_SIZE(uart_config)) + type = 0; + return uart_config[type].name; +} + +static struct uart_ops serialsio_pops = { + .tx_empty = serialsio_tx_empty, + .set_mctrl = serialsio_set_mctrl, + .get_mctrl = serialsio_get_mctrl, + .stop_tx = serialsio_stop_tx, + .start_tx = serialsio_start_tx, + .stop_rx = serialsio_stop_rx, + .enable_ms = serialsio_enable_ms, + .break_ctl = serialsio_break_ctl, + .startup = serialsio_startup, + .shutdown = serialsio_shutdown, + .set_termios = serialsio_set_termios, + .pm = serialsio_pm, + .type = serialsio_type, + .release_port = serialsio_release_port, + .request_port = serialsio_request_port, + .config_port = serialsio_config_port, + .verify_port = serialsio_verify_port, +}; + +static struct uart_sio_port serialsio_ports[UART_NR]; + +static void __init serialsio_isa_init_ports(void) +{ + struct uart_sio_port *up; + static int first = 1; + int i; + + if (!first) + return; + first = 0; + + for (i = 0, up = serialsio_ports; i < ARRAY_SIZE(old_serial_port); + i++, up++) { + up->port.iobase = old_serial_port[i].port; + up->port.irq = irq_canonicalize(old_serial_port[i].irq); + up->port.uartclk = old_serial_port[i].baud_base * 16; + up->port.flags = old_serial_port[i].flags; + up->port.hub6 = old_serial_port[i].hub6; + up->port.membase = old_serial_port[i].iomem_base; + up->port.iotype = old_serial_port[i].io_type; + up->port.regshift = old_serial_port[i].iomem_reg_shift; + up->port.ops = &serialsio_pops; + if (share_irqs_sio) + up->port.flags |= UPF_SHARE_IRQ; + } +} + +static void __init serialsio_register_ports(struct uart_driver *drv) +{ + int i; + + serialsio_isa_init_ports(); + + for (i = 0; i < UART_NR; i++) { + struct uart_sio_port *up = &serialsio_ports[i]; + + up->port.line = i; + up->port.ops = &serialsio_pops; + init_timer(&up->timer); + up->timer.function = serialsio_timeout; + + /* + * ALPHA_KLUDGE_MCR needs to be killed. + */ + up->mcr_mask = ~ALPHA_KLUDGE_MCR; + up->mcr_force = ALPHA_KLUDGE_MCR; + + uart_add_one_port(drv, &up->port); + } +} + +#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +/* + * Wait for transmitter & holding register to empty + */ +static __inline__ void wait_for_xmitr(struct uart_sio_port *up) +{ + unsigned int status, tmout = 10000; + + /* Wait up to 10ms for the character(s) to be sent. */ + do { + status = sio_in(up, SIOSTS); + + if (--tmout == 0) + break; + udelay(1); + } while ((status & BOTH_EMPTY) != BOTH_EMPTY); + + /* Wait up to 1s for flow control if necessary */ + if (up->port.flags & UPF_CONS_FLOW) { + tmout = 1000000; + while (--tmout) + udelay(1); + } +} + +/* + * Print a string to the serial port trying not to disturb + * any possible real use of the port... + * + * The console_lock must be held when we get here. + */ +static void serialsio_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_sio_port *up = &serialsio_ports[co->index]; + unsigned int ier; + int i; + + /* + * First save the UER then disable the interrupts + */ + ier = sio_in(up, SIOTRCR); + sio_out(up, SIOTRCR, 0); + + /* + * Now, do each character + */ + for (i = 0; i < count; i++, s++) { + wait_for_xmitr(up); + + /* + * Send the character out. + * If a LF, also do CR... + */ + sio_out(up, SIOTXB, *s); + + if (*s == 10) { + wait_for_xmitr(up); + sio_out(up, SIOTXB, 13); + } + } + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + wait_for_xmitr(up); + sio_out(up, SIOTRCR, ier); +} + +static int __init serialsio_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index >= UART_NR) + co->index = 0; + port = &serialsio_ports[co->index].port; + + /* + * Temporary fix. + */ + spin_lock_init(&port->lock); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +extern struct uart_driver serialsio_reg; +static struct console serialsio_console = { + .name = "ttyD", + .write = serialsio_console_write, + .device = uart_console_device, + .setup = serialsio_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &serialsio_reg, +}; + +static int __init serialsio_console_init(void) +{ + sio_reset(); + sio_init(); + serialsio_isa_init_ports(); + register_console(&serialsio_console); + return 0; +} +console_initcall(serialsio_console_init); + +#define SERIALSIO_CONSOLE &serialsio_console +#else +#define SERIALSIO_CONSOLE NULL +#endif + +static struct uart_driver serialsio_reg = { + .owner = THIS_MODULE, + .driver_name = "sio", + .devfs_name = "tts/", + .dev_name = "ttyD", + .major = TTY_MAJOR, + .minor = 80, + .nr = UART_NR, + .cons = SERIALSIO_CONSOLE, +}; + +/* + * register_serial and unregister_serial allows for 16x50 serial ports to be + * configured at run-time, to support PCMCIA modems. + */ + +static int __register_serialsio(struct serial_struct *req, int line) +{ + struct uart_port port; + + port.iobase = req->port; + port.membase = req->iomem_base; + port.irq = req->irq; + port.uartclk = req->baud_base * 16; + port.fifosize = req->xmit_fifo_size; + port.regshift = req->iomem_reg_shift; + port.iotype = req->io_type; + port.flags = req->flags | UPF_BOOT_AUTOCONF; + port.mapbase = req->iomap_base; + port.line = line; + + if (share_irqs_sio) + port.flags |= UPF_SHARE_IRQ; + + if (HIGH_BITS_OFFSET) + port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET; + + /* + * If a clock rate wasn't specified by the low level + * driver, then default to the standard clock rate. + */ + if (port.uartclk == 0) + port.uartclk = BASE_BAUD * 16; + + return uart_register_port(&serialsio_reg, &port); +} + +/** + * register_serial - configure a 16x50 serial port at runtime + * @req: request structure + * + * Configure the serial port specified by the request. If the + * port exists and is in use an error is returned. If the port + * is not currently in the table it is added. + * + * The port is then probed and if necessary the IRQ is autodetected + * If this fails an error is returned. + * + * On success the port is ready to use and the line number is returned. + */ +int register_serialsio(struct serial_struct *req) +{ + return __register_serialsio(req, -1); +} + +int __init early_serialsio_setup(struct uart_port *port) +{ + serialsio_isa_init_ports(); + serialsio_ports[port->line].port = *port; + serialsio_ports[port->line].port.ops = &serialsio_pops; + + return 0; +} + +/** + * unregister_serial - remove a 16x50 serial port at runtime + * @line: serial line number + * + * Remove one serial port. This may be called from interrupt + * context. + */ +void unregister_serialsio(int line) +{ + uart_unregister_port(&serialsio_reg, line); +} + +/* + * This is for ISAPNP only. + */ +void serialsio_get_irq_map(unsigned int *map) +{ + int i; + + for (i = 0; i < UART_NR; i++) { + if (serialsio_ports[i].port.type != PORT_UNKNOWN && + serialsio_ports[i].port.irq < 16) + *map |= 1 << serialsio_ports[i].port.irq; + } +} + +/** + * serialsio_suspend_port - suspend one serial port + * @line: serial line number + * + * Suspend one serial port. + */ +void serialsio_suspend_port(int line) +{ + uart_suspend_port(&serialsio_reg, &serialsio_ports[line].port); +} + +/** + * serialsio_resume_port - resume one serial port + * @line: serial line number + * + * Resume one serial port. + */ +void serialsio_resume_port(int line) +{ + uart_resume_port(&serialsio_reg, &serialsio_ports[line].port); +} + +static int __init serialsio_init(void) +{ + int ret, i; + + printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.4 $ " + "IRQ sharing %sabled\n", share_irqs_sio ? "en" : "dis"); + + for (i = 0; i < NR_IRQS; i++) + spin_lock_init(&irq_lists[i].lock); + + ret = uart_register_driver(&serialsio_reg); + if (ret >= 0) + serialsio_register_ports(&serialsio_reg); + + return ret; +} + +static void __exit serialsio_exit(void) +{ + int i; + + for (i = 0; i < UART_NR; i++) + uart_remove_one_port(&serialsio_reg, &serialsio_ports[i].port); + + uart_unregister_driver(&serialsio_reg); +} + +module_init(serialsio_init); +module_exit(serialsio_exit); + +EXPORT_SYMBOL(register_serialsio); +EXPORT_SYMBOL(unregister_serialsio); +EXPORT_SYMBOL(serialsio_get_irq_map); +EXPORT_SYMBOL(serialsio_suspend_port); +EXPORT_SYMBOL(serialsio_resume_port); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.4 $"); + +MODULE_PARM(share_irqs_sio, "i"); +MODULE_PARM_DESC(share_irqs_sio, "Share IRQs with other non-M32R SIO devices" + " (unsafe)"); + diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/m32r_sio.h linux-2.6.8.1/drivers/serial/m32r_sio.h --- linux-2.6.8.1.org/drivers/serial/m32r_sio.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/m32r_sio.h 2004-04-05 11:33:48.000000000 +0900 @@ -0,0 +1,58 @@ +/* + * linux/drivers/char/8250.h + * + * Driver for 8250/16550-type serial ports + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * Copyright (C) 2001 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * $Id: m32r_sio.h,v 1.1.1.1 2004/03/25 04:29:01 hitoshiy Exp $ + */ + +#include + +struct serialsio_probe { + struct module *owner; + int (*pci_init_one)(struct pci_dev *dev); + void (*pci_remove_one)(struct pci_dev *dev); + void (*pnp_init)(void); +}; + +int serialsio_register_probe(struct serialsio_probe *probe); +void serialsio_unregister_probe(struct serialsio_probe *probe); +void serialsio_get_irq_map(unsigned int *map); +void serialsio_suspend_port(int line); +void serialsio_resume_port(int line); + +struct old_serial_port { + unsigned int uart; + unsigned int baud_base; + unsigned int port; + unsigned int irq; + unsigned int flags; + unsigned char hub6; + unsigned char io_type; + unsigned char *iomem_base; + unsigned short iomem_reg_shift; +}; + +#undef SERIAL_DEBUG_PCI + +#define _INLINE_ __inline__ + +#define PROBE_RSA (1 << 0) +#define PROBE_ANY (~0) + +#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) + +#ifdef CONFIG_SERIAL_SIO_SHARE_IRQ +#define SERIALSIO_SHARE_IRQS 1 +#else +#define SERIALSIO_SHARE_IRQS 0 +#endif diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/serial/m32r_sio_reg.h linux-2.6.8.1/drivers/serial/m32r_sio_reg.h --- linux-2.6.8.1.org/drivers/serial/m32r_sio_reg.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/serial/m32r_sio_reg.h 2004-03-25 13:29:01.000000000 +0900 @@ -0,0 +1,292 @@ +/* + * include/linux/m32r_sio_reg.h + * + * Copyright (C) 1992, 1994 by Theodore Ts'o. + * + * Redistribution of this file is permitted under the terms of the GNU + * Public License (GPL) + * + * These are the UART port assignments, expressed as offsets from the base + * register. These assignments should hold for any serial port based on + * a 8250, 16450, or 16550(A). + */ + +#ifndef _M32R_SIO_REG_H +#define _M32R_SIO_REG_H + +#define SIOCR 0x000 +#define SIOMOD0 0x004 +#define SIOMOD1 0x008 +#define SIOSTS 0x00c +#define SIOTRCR 0x010 +#define SIOBAUR 0x014 +#define SIORBAUR 0x018 +#define SIOTXB 0x01c +#define SIORXB 0x020 + +#define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */ +#define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels + * XR16C85x only */ + +#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */ +#define UART_FCTR 0 /* (LCR=BF) Feature Control Register + * XR16C85x only */ + +#define UART_IIR 0 /* In: Interrupt ID Register */ +#define UART_FCR 0 /* Out: FIFO Control Register */ +#define UART_EFR 0 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ + +#define UART_LCR 0 /* Out: Line Control Register */ +#define UART_MCR 0 /* Out: Modem Control Register */ +#define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */ +#define UART_MSR 0 /* In: Modem Status Register */ +#define UART_SCR 0 /* I/O: Scratch Register */ +#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register + * FCTR bit 6 selects SCR or EMSR + * XR16c85x only */ + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 redefinitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ +/* TI 16750 definitions */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x02 /* Transmitter empty */ +#define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x00 /* Break interrupt indicator */ +#define UART_LSR_FE 0x80 /* Frame error indicator */ +#define UART_LSR_PE 0x40 /* Parity error indicator */ +#define UART_LSR_OE 0x20 /* Overrun error indicator */ +#define UART_LSR_DR 0x04 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x00 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x04 /* Enable receiver data interrupt */ +/* + * Sleep mode for ST16650 and TI16750. + * Note that for 16650, EFR-bit 4 must be selected as well. + */ +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +/* + * These are the definitions for the Extended Features Register + * (StarTech 16C660 only, when DLAB=1) + */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ECB 0x10 /* Enhanced control bit */ +/* + * the low four bits control software flow control + */ + +/* + * These register definitions are for the 16C950 + */ +#define UART_ASR 0x01 /* Additional Status Register */ +#define UART_RFL 0x03 /* Receiver FIFO level */ +#define UART_TFL 0x04 /* Transmitter FIFO level */ +#define UART_ICR 0x05 /* Index Control Register */ + +/* The 16950 ICR registers */ +#define UART_ACR 0x00 /* Additional Control Register */ +#define UART_CPR 0x01 /* Clock Prescalar Register */ +#define UART_TCR 0x02 /* Times Clock Register */ +#define UART_CKS 0x03 /* Clock Select Register */ +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ +#define UART_FCL 0x06 /* Flow Control Level Lower */ +#define UART_FCH 0x07 /* Flow Control Level Higher */ +#define UART_ID1 0x08 /* ID #1 */ +#define UART_ID2 0x09 /* ID #2 */ +#define UART_ID3 0x0A /* ID #3 */ +#define UART_REV 0x0B /* Revision */ +#define UART_CSR 0x0C /* Channel Software Reset */ +#define UART_NMR 0x0D /* Nine-bit Mode Register */ +#define UART_CTR 0xFF + +/* + * The 16C950 Additional Control Reigster + */ +#define UART_ACR_RXDIS 0x01 /* Receiver disable */ +#define UART_ACR_TXDIS 0x02 /* Receiver disable */ +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */ +#define UART_ACR_ASREN 0x80 /* Additional status enable */ + +/* + * These are the definitions for the Feature Control Register + * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable + * Register, UART register #1) + */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ + +/* + * These are the definitions for the Enhanced Mode Select Register + * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the + * Scratch register, UART register #7) + */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ + +/* + * These are the definitions for the Programmable Trigger + * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX + * register, UART register #0) + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 + +/* + * These definitions are for the RSA-DV II/S card, from + * + * Kiyokazu SUTO + */ + +#define UART_RSA_BASE (-8) + +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ + +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ + +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ + +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ + +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ + +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ + +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ + +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ + +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ + +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ + +/* + * The RSA DSV/II board has two fixed clock frequencies. One is the + * standard rate, and the other is 8 times faster. + */ +#define SERIAL_RSA_BAUD_BASE (921600) +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) + +#endif /* _M32R_SIO_REG_H */ + diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/Kconfig linux-2.6.8.1/drivers/video/Kconfig --- linux-2.6.8.1.org/drivers/video/Kconfig 2004-08-14 19:54:47.000000000 +0900 +++ linux-2.6.8.1/drivers/video/Kconfig 2004-08-30 10:24:03.000000000 +0900 @@ -421,6 +421,12 @@ for discussion. +config FB_EPSON_S1D13806 + bool "Epson 13806 framebuffer support" + depends on FB && M32R + help + EPSON S1D13806 Driver + config FB_RIVA tristate "nVidia Riva support" depends on FB && PCI diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/Makefile linux-2.6.8.1/drivers/video/Makefile --- linux-2.6.8.1.org/drivers/video/Makefile 2004-08-14 19:54:50.000000000 +0900 +++ linux-2.6.8.1/drivers/video/Makefile 2004-08-30 10:24:03.000000000 +0900 @@ -70,6 +70,7 @@ obj-$(CONFIG_FB_VIRTUAL) += vfb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o obj-$(CONFIG_FB_HIT) += hitfb.o cfbfillrect.o cfbimgblt.o obj-$(CONFIG_FB_E1355) += epson1355fb.o +obj-$(CONFIG_FB_EPSON_S1D13806) += s1d13xxxfb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o obj-$(CONFIG_FB_PVR2) += pvr2fb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o obj-$(CONFIG_FB_KYRO) += kyro/ cfbfillrect.o cfbcopyarea.o cfbimgblt.o obj-$(CONFIG_FB_VOODOO1) += sstfb.o cfbfillrect.o cfbcopyarea.o cfbimgblt.o diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/fbmem.c linux-2.6.8.1/drivers/video/fbmem.c --- linux-2.6.8.1.org/drivers/video/fbmem.c 2004-08-14 19:54:46.000000000 +0900 +++ linux-2.6.8.1/drivers/video/fbmem.c 2004-08-30 10:24:03.000000000 +0900 @@ -174,6 +174,9 @@ extern int mc68x328fb_setup(char *); extern int asiliantfb_init(void); +extern int s1d13xxxfb_init(void); +extern int s1d13xxxfb_setup(char *); + static struct { const char *name; int (*init)(void); @@ -390,6 +393,10 @@ { "asiliantfb", asiliantfb_init, NULL }, #endif +#ifdef CONFIG_FB_EPSON_S1D13806 + { "s1d13xxxfb", s1d13xxxfb_init, s1d13xxxfb_setup }, +#endif + /* * Generic drivers that don't use resource management (yet) */ @@ -1290,6 +1297,8 @@ pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; #elif defined(__ia64__) || defined(__arm__) || defined(__sh__) vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +#elif defined(__m32r__) + pgprot_val(vma->vm_page_prot) |= _PAGE_NONCACHABLE; #else #warning What do we have to do here?? #endif diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/logo/Kconfig linux-2.6.8.1/drivers/video/logo/Kconfig --- linux-2.6.8.1.org/drivers/video/logo/Kconfig 2004-08-14 19:55:20.000000000 +0900 +++ linux-2.6.8.1/drivers/video/logo/Kconfig 2004-06-24 09:40:51.000000000 +0900 @@ -63,5 +63,10 @@ depends on LOGO && SUPERH default y +config LOGO_M32R_CLUT224 + bool "224-color M32R Linux logo" + depends on LOGO && M32R + default y + endmenu diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/logo/Makefile linux-2.6.8.1/drivers/video/logo/Makefile --- linux-2.6.8.1.org/drivers/video/logo/Makefile 2004-08-14 19:55:48.000000000 +0900 +++ linux-2.6.8.1/drivers/video/logo/Makefile 2004-06-24 09:40:51.000000000 +0900 @@ -12,6 +12,7 @@ obj-$(CONFIG_LOGO_SUPERH_MONO) += logo_superh_mono.o obj-$(CONFIG_LOGO_SUPERH_VGA16) += logo_superh_vga16.o obj-$(CONFIG_LOGO_SUPERH_CLUT224) += logo_superh_clut224.o +obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o # How to generate logo's diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/logo/logo.c linux-2.6.8.1/drivers/video/logo/logo.c --- linux-2.6.8.1.org/drivers/video/logo/logo.c 2004-08-14 19:55:33.000000000 +0900 +++ linux-2.6.8.1/drivers/video/logo/logo.c 2004-08-30 10:24:03.000000000 +0900 @@ -32,6 +32,7 @@ extern const struct linux_logo logo_superh_mono; extern const struct linux_logo logo_superh_vga16; extern const struct linux_logo logo_superh_clut224; +extern const struct linux_logo logo_m32r_clut224; const struct linux_logo *fb_find_logo(int depth) @@ -94,6 +95,10 @@ /* SuperH Linux logo */ logo = &logo_superh_clut224; #endif +#ifdef CONFIG_LOGO_M32R_CLUT224 + /* M32R Linux logo */ + logo = &logo_m32r_clut224; +#endif } return logo; } diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/logo/logo_m32r_clut224.ppm linux-2.6.8.1/drivers/video/logo/logo_m32r_clut224.ppm --- linux-2.6.8.1.org/drivers/video/logo/logo_m32r_clut224.ppm 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/video/logo/logo_m32r_clut224.ppm 2004-06-24 09:40:51.000000000 +0900 @@ -0,0 +1,1603 @@ +P3 +80 80 +255 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +12 10 12 12 10 12 12 10 12 12 10 12 +12 10 12 4 2 4 12 10 12 12 10 12 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 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12 172 118 4 +76 54 12 4 2 4 4 6 4 28 30 28 +52 54 52 60 62 60 52 50 52 36 38 36 +12 14 12 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 76 54 12 164 114 4 +212 154 12 236 178 12 244 190 12 244 190 12 +244 190 12 244 190 12 244 190 12 244 190 12 +244 190 12 244 186 12 236 182 12 236 182 12 +228 174 12 212 150 12 172 134 52 124 114 92 +84 82 84 52 54 52 28 30 28 20 18 20 +4 6 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 6 4 20 18 20 +44 46 44 156 118 36 196 134 12 188 146 12 +220 158 12 220 162 12 228 166 12 228 170 12 +228 174 12 236 178 12 236 182 12 236 182 12 +236 186 12 244 186 12 244 190 12 244 190 12 +244 190 12 244 190 12 244 190 12 244 190 12 +244 186 12 228 174 12 212 150 12 156 114 12 +108 70 4 12 10 12 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 6 4 92 62 4 172 118 4 +204 146 12 228 170 12 244 186 12 244 190 12 +244 190 12 244 190 12 244 186 12 244 186 12 +236 182 12 228 170 12 228 166 12 212 154 12 +180 134 36 124 114 92 84 86 84 60 58 60 +36 38 36 20 22 20 12 10 12 4 6 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 12 14 12 +36 34 36 68 70 68 140 110 52 156 118 36 +164 114 4 180 122 4 196 134 12 196 138 12 +196 138 12 212 150 12 212 154 12 228 166 12 +228 166 12 228 174 12 236 182 12 244 186 12 +244 186 12 244 186 12 244 186 12 244 186 12 +236 182 12 220 158 12 188 134 12 156 98 4 +108 70 4 12 14 12 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 6 4 76 54 12 156 98 4 +188 134 12 220 162 12 236 178 12 236 182 12 +244 186 12 244 186 12 236 182 12 236 178 12 +228 166 12 204 146 12 188 134 12 156 122 60 +92 94 92 60 62 60 44 42 44 20 22 20 +12 14 12 4 6 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 6 4 +20 18 20 36 34 36 60 58 60 76 78 76 +100 98 92 124 114 92 140 110 44 156 106 12 +164 114 4 156 114 12 172 118 4 180 122 4 +188 134 12 196 138 12 212 150 12 220 162 12 +228 170 12 236 178 12 236 178 12 236 178 12 +220 162 12 196 138 12 164 110 12 124 82 4 +92 62 4 12 10 12 4 2 4 4 2 4 +20 18 20 36 38 36 36 38 36 36 38 36 +44 42 44 36 38 36 44 42 44 36 38 36 +36 38 36 36 38 36 28 26 28 4 2 4 +4 2 4 4 6 4 68 46 4 140 94 4 +172 118 4 204 146 12 220 158 12 228 174 12 +236 174 12 228 174 12 220 162 12 212 150 12 +188 134 12 164 114 4 124 114 92 84 82 84 +52 50 52 28 30 28 12 14 12 4 6 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 6 4 12 14 12 20 22 20 36 34 36 +44 42 44 60 58 60 76 74 76 84 86 84 +100 98 92 124 102 68 132 98 44 124 86 28 +132 86 4 156 98 4 164 114 4 172 118 4 +188 134 12 196 134 12 204 146 12 196 138 12 +180 122 4 156 106 12 132 82 4 108 70 4 +52 34 4 52 54 52 108 110 108 100 98 92 +84 86 84 84 82 84 76 78 76 76 78 76 +76 78 76 76 78 76 76 78 76 76 78 76 +76 78 76 84 82 84 84 86 84 92 94 92 +108 106 108 100 102 100 84 66 36 124 82 4 +156 106 12 180 122 4 196 134 12 196 138 12 +212 150 12 196 138 12 188 134 12 172 118 4 +140 102 12 108 106 92 68 70 68 44 42 44 +20 22 20 4 6 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 6 4 4 6 4 +12 14 12 20 22 20 28 30 28 44 42 44 +52 50 52 60 62 60 76 74 76 92 90 92 +100 98 92 116 102 76 124 86 28 124 82 4 +140 94 4 140 102 12 156 98 4 156 98 4 +140 86 4 116 82 12 100 70 4 84 66 28 +100 98 92 84 82 84 60 58 60 44 46 44 +44 42 44 36 34 36 36 34 36 36 34 36 +36 34 36 28 30 28 36 38 36 36 34 36 +36 34 36 36 34 36 36 38 36 44 42 44 +52 54 52 84 82 84 92 86 76 92 62 4 +132 86 4 156 106 12 172 118 4 172 118 4 +172 118 4 172 118 4 156 98 4 124 86 28 +100 98 92 60 62 60 36 34 36 20 18 20 +4 6 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 6 4 4 6 4 4 6 4 +20 18 20 20 22 20 28 30 28 44 42 44 +44 46 44 68 66 68 84 86 84 100 98 92 +108 86 60 100 70 4 100 70 4 108 70 4 +100 70 4 92 62 4 84 62 36 92 90 92 +60 62 60 36 38 36 20 22 20 12 14 12 +4 6 4 12 10 12 4 6 4 12 10 12 +4 6 4 12 10 12 4 6 4 4 6 4 +12 10 12 4 6 4 12 10 12 12 14 12 +20 22 20 36 38 36 68 70 68 92 82 68 +76 54 12 100 70 4 116 82 12 140 94 4 +132 86 4 116 82 12 100 82 52 84 86 84 +60 58 60 28 30 28 12 14 12 4 6 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 6 4 4 6 4 12 14 12 +20 18 20 28 26 28 36 38 36 52 54 52 +68 70 68 84 86 84 92 86 76 92 82 68 +92 82 68 84 86 84 76 74 76 52 50 52 +28 30 28 12 14 12 4 6 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 6 4 20 18 20 36 34 36 60 58 60 +84 82 84 92 82 68 92 82 68 92 82 68 +92 86 68 92 86 76 76 74 76 52 50 52 +28 26 28 12 14 12 4 6 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 6 4 4 6 4 12 14 12 20 18 20 +36 34 36 36 38 36 44 46 44 52 54 52 +52 50 52 44 42 44 28 30 28 20 18 20 +4 6 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 6 4 12 14 12 28 26 28 +36 38 36 52 50 52 60 58 60 60 58 60 +52 54 52 44 42 44 28 30 28 20 18 20 +4 6 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 6 4 +4 6 4 12 10 12 12 14 12 20 18 20 +20 18 20 12 14 12 12 10 12 4 6 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 6 4 +12 14 12 20 18 20 20 22 20 20 22 20 +20 18 20 12 14 12 12 10 12 4 6 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 +4 2 4 4 2 4 4 2 4 4 2 4 diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/s1d13806.h linux-2.6.8.1/drivers/video/s1d13806.h --- linux-2.6.8.1.org/drivers/video/s1d13806.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/video/s1d13806.h 2004-08-17 09:40:05.000000000 +0900 @@ -0,0 +1,310 @@ +//---------------------------------------------------------------------------- +// +// File generated by S1D13806CFG.EXE +// +// Copyright (c) 2000,2001 Epson Research and Development, Inc. +// All rights reserved. +// +//---------------------------------------------------------------------------- + +// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz) +// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz) + +#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */ + +#if defined(CONFIG_PLAT_MAPPI) + +#define DEFAULT_MODE "640x480-8" +#define S1D_PHYSICAL_VMEM_ADDR 0x10200000L +#define S1D_PHYSICAL_VMEM_SIZE 0x00140000L +#define S1D_PHYSICAL_REG_ADDR 0x10000000L +#define S1D_PHYSICAL_REG_SIZE 0x200 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + +// M3T-M32RUT-LCD +// 320x240, BUSCLK:45.1584MHz, CLKI:22.5792MHz +#define DEFAULT_MODE "240x320-16" +#define S1D_PHYSICAL_VMEM_ADDR 0x10600000L +#define S1D_PHYSICAL_VMEM_SIZE 0x00140000L /* Image,Cursor,Panel Buffer */ +#define S1D_PHYSICAL_REG_ADDR 0x10400000L +#define S1D_PHYSICAL_REG_SIZE 0x200 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#else +#error no platform configuration +#endif + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(r); \ + ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(g); \ + ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(b); \ +} + +#define S1D_READ_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + r = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ + g = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ + b = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)]; \ +} + +typedef unsigned short S1D_INDEX; +typedef unsigned char S1D_VALUE; + +typedef struct +{ + S1D_INDEX Index; + S1D_VALUE Value; +} S1D_REGS; + +static S1D_REGS aS1DRegs_common[] = +{ + {0x0001,0x00}, // Miscellaneous Register + {0x01FC,0x00}, // Display Mode Register +#if defined(CONFIG_PLAT_MAPPI) + {0x0004,0x00}, // General IO Pins Configuration Register 0 + {0x0005,0x00}, // General IO Pins Configuration Register 1 + {0x0008,0x00}, // General IO Pins Control Register 0 + {0x0009,0x00}, // General IO Pins Control Register 1 + {0x0010,0x00}, // Memory Clock Configuration Register + {0x0014,0x00}, // LCD Pixel Clock Configuration Register + {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register + {0x001C,0x00}, // MediaPlug Clock Configuration Register +/* + * .. 10MHz: 0x00 + * .. 30MHz: 0x01 + * 30MHz ..: 0x02 + */ + {0x001E,0x02}, // CPU To Memory Wait State Select Register + {0x0021,0x02}, // DRAM Refresh Rate Register + {0x002A,0x11}, // DRAM Timings Control Register 0 + {0x002B,0x13}, // DRAM Timings Control Register 1 + {0x0020,0x80}, // Memory Configuration Register + {0x0030,0x25}, // Panel Type Register + {0x0031,0x00}, // MOD Rate Register + {0x0032,0x4F}, // LCD Horizontal Display Width Register + {0x0034,0x12}, // LCD Horizontal Non-Display Period Register + {0x0035,0x01}, // TFT FPLINE Start Position Register + {0x0036,0x0B}, // TFT FPLINE Pulse Width Register + {0x0038,0xDF}, // LCD Vertical Display Height Register 0 + {0x0039,0x01}, // LCD Vertical Display Height Register 1 + {0x003A,0x2C}, // LCD Vertical Non-Display Period Register + {0x003B,0x0A}, // TFT FPFRAME Start Position Register + {0x003C,0x01}, // TFT FPFRAME Pulse Width Register + + {0x0041,0x00}, // LCD Miscellaneous Register + {0x0042,0x00}, // LCD Display Start Address Register 0 + {0x0043,0x00}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + {0x0004,0x07}, // GPIO[0:7] direction + {0x0005,0x00}, // GPIO[8:12] direction + {0x0008,0x00}, // GPIO[0:7] data + {0x0009,0x00}, // GPIO[8:12] data + {0x0008,0x04}, // LCD panel Vcc on + {0x0008,0x05}, // LCD panel reset + {0x0010,0x01}, // Memory Clock Configuration Register + {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4) + {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register + {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz) + {0x001E,0x00}, // CPU To Memory Wait State Select Register + {0x0020,0x80}, // Memory Configuration Register + {0x0021,0x03}, // DRAM Refresh Rate Register + {0x002A,0x00}, // DRAM Timings Control Register 0 + {0x002B,0x01}, // DRAM Timings Control Register 1 + {0x0030,0x25}, // Panel Type Register + {0x0031,0x00}, // MOD Rate Register + {0x0032,0x1d}, // LCD Horizontal Display Width Register + {0x0034,0x05}, // LCD Horizontal Non-Display Period Register + {0x0035,0x01}, // TFT FPLINE Start Position Register + {0x0036,0x01}, // TFT FPLINE Pulse Width Register + {0x0038,0x3F}, // LCD Vertical Display Height Register 0 + {0x0039,0x01}, // LCD Vertical Display Height Register 1 + {0x003A,0x0b}, // LCD Vertical Non-Display Period Register + {0x003B,0x07}, // TFT FPFRAME Start Position Register + {0x003C,0x02}, // TFT FPFRAME Pulse Width Register + + {0x0041,0x00}, // LCD Miscellaneous Register +#if (SWIVEL_VIEW == 0) + {0x0042,0x00}, // LCD Display Start Address Register 0 + {0x0043,0x00}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + +#elif (SWIVEL_VIEW == 1) + // 1024 - W(320) = 0x2C0 + {0x0042,0xC0}, // LCD Display Start Address Register 0 + {0x0043,0x02}, // LCD Display Start Address Register 1 + {0x0044,0x00}, // LCD Display Start Address Register 2 + // 1024 + {0x0046,0x00}, // LCD Memory Address Offset Register 0 + {0x0047,0x02}, // LCD Memory Address Offset Register 1 +#else +#error unsupported SWIVEL_VIEW mode +#endif +#else +#error no platform configuration +#endif /* CONFIG_PLAT_XXX */ + + {0x0048,0x00}, // LCD Pixel Panning Register + {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register + {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register + {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register + {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register + {0x0053,0x01}, // CRT/TV HRTC Start Position Register + {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register + {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 + {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 + {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register + {0x0059,0x09}, // CRT/TV VRTC Start Position Register + {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register + {0x005B,0x10}, // TV Output Control Register + + {0x0062,0x00}, // CRT/TV Display Start Address Register 0 + {0x0063,0x00}, // CRT/TV Display Start Address Register 1 + {0x0064,0x00}, // CRT/TV Display Start Address Register 2 + + {0x0068,0x00}, // CRT/TV Pixel Panning Register + {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register + {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register + {0x0070,0x00}, // LCD Ink/Cursor Control Register + {0x0071,0x01}, // LCD Ink/Cursor Start Address Register + {0x0072,0x00}, // LCD Cursor X Position Register 0 + {0x0073,0x00}, // LCD Cursor X Position Register 1 + {0x0074,0x00}, // LCD Cursor Y Position Register 0 + {0x0075,0x00}, // LCD Cursor Y Position Register 1 + {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register + {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register + {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register + {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register + {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register + {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register + {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register + {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register + {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register + {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 + {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 + {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 + {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 + {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register + {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register + {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register + {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register + {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register + {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register + {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register + {0x0100,0x00}, // BitBlt Control Register 0 + {0x0101,0x00}, // BitBlt Control Register 1 + {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register + {0x0103,0x00}, // BitBlt Operation Register + {0x0104,0x00}, // BitBlt Source Start Address Register 0 + {0x0105,0x00}, // BitBlt Source Start Address Register 1 + {0x0106,0x00}, // BitBlt Source Start Address Register 2 + {0x0108,0x00}, // BitBlt Destination Start Address Register 0 + {0x0109,0x00}, // BitBlt Destination Start Address Register 1 + {0x010A,0x00}, // BitBlt Destination Start Address Register 2 + {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 + {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 + {0x0110,0x00}, // BitBlt Width Register 0 + {0x0111,0x00}, // BitBlt Width Register 1 + {0x0112,0x00}, // BitBlt Height Register 0 + {0x0113,0x00}, // BitBlt Height Register 1 + {0x0114,0x00}, // BitBlt Background Color Register 0 + {0x0115,0x00}, // BitBlt Background Color Register 1 + {0x0118,0x00}, // BitBlt Foreground Color Register 0 + {0x0119,0x00}, // BitBlt Foreground Color Register 1 + {0x01E0,0x00}, // Look-Up Table Mode Register + {0x01E2,0x00}, // Look-Up Table Address Register + {0x01F0,0x10}, // Power Save Configuration Register + {0x01F1,0x00}, // Power Save Status Register + {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register +#if (SWIVEL_VIEW == 0) + {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) +#elif (SWIVEL_VIEW == 1) + {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) +#else +#error unsupported SWIVEL_VIEW mode +#endif /* SWIVEL_VIEW */ + +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + {0x0008,0x07}, // LCD panel Vdd & Vg on +#endif +}; + + +static S1D_REGS aS1DRegs_4bpp[] = +{ + {0x0040,0x02}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) +#if defined(CONFIG_PLAT_MAPPI) + {0x0046,0xa0}, // LCD Memory Address Offset Register 0 + {0x0047,0x00}, // LCD Memory Address Offset Register 1 +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + {0x0046,0x3c}, // LCD Memory Address Offset Register 0 + {0x0047,0x00}, // LCD Memory Address Offset Register 1 +#endif + {0x0060,0x02}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) + {0x0066,0xa0}, // CRT/TV Memory Address Offset Register 0 // takeo + {0x0067,0x00}, // CRT/TV Memory Address Offset Register 1 +}; + +static S1D_REGS aS1DRegs_8bpp[] = +{ + {0x0040,0x03}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) +#if defined(CONFIG_PLAT_MAPPI) + {0x0046,0x40}, // LCD Memory Address Offset Register 0 + {0x0047,0x01}, // LCD Memory Address Offset Register 1 +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + {0x0046,0x78}, // LCD Memory Address Offset Register 0 + {0x0047,0x00}, // LCD Memory Address Offset Register 1 +#endif + {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) + {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 // takeo + {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 +}; + +static S1D_REGS aS1DRegs_16bpp[] = +{ + {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) +#if defined(CONFIG_PLAT_MAPPI) + {0x0046,0x80}, // LCD Memory Address Offset Register 0 + {0x0047,0x02}, // LCD Memory Address Offset Register 1 +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + {0x0046,0xf0}, // LCD Memory Address Offset Register 0 + {0x0047,0x00}, // LCD Memory Address Offset Register 1 +#endif + {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) + {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo + {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1 +}; + +#define DEFAULT_MODEDB_INDEX 0 + +static const struct fb_videomode m32r_modedb[] = { + { + /* 640x480, 77 Hz, Non-Interlaced (25.175 MHz dotclock) */ + "mappi_lcd", 77, 640, 480, 25175, 0, 0, 0, 0, 0, 0, + 0, FB_VMODE_NONINTERLACED + }, { + /* 240x320, 60 Hz, Non-Interlaced (22.579 MHz dotclock) */ + "ut_lcd", 60, 240, 320, 22579, 0, 0, 0, 0, 0, 0, + 0, FB_VMODE_NONINTERLACED + }, { + /* 640x480 @ 60 Hz, 31.5 kHz hsync */ + "mappi_crt", 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, + 0, FB_VMODE_NONINTERLACED + }, { + /* 800x600 60Hz (PCLK=CLKI=40.000MHz) ? */ + "mappi_crt2", 60, 800, 600, 40000, 40, 24, 32, 11, 96, 2, + 0, FB_VMODE_NONINTERLACED + }, +}; + + diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/drivers/video/s1d13xxxfb.c linux-2.6.8.1/drivers/video/s1d13xxxfb.c --- linux-2.6.8.1.org/drivers/video/s1d13xxxfb.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.8.1/drivers/video/s1d13xxxfb.c 2004-08-17 09:40:05.000000000 +0900 @@ -0,0 +1,637 @@ +//----------------------------------------------------------------------------- +// +// linux/drivers/video/s1d13xxxfb.c -- frame buffer driver for Epson S1D13xxx +// +// Copyright(c) 2000, 2001 Epson Research and Development, Inc. +// All rights reserved. +// fixed for 2.4 by Hiroyuki Kondo +// fixed for 2.6 by Hayato FUJIWARA +// +//---------------------------------------------------------------------------- +// +// This driver supports one of the following Epson CRT/TV/LCD controllers: +// +// S1D13504 +// S1D13505 +// S1D13506 +// S1D13704 +// S1D13705 +// S1D13706 +// S1D13806 +// S1D13A03 +// +// The intended platforms for this driver are embedded systems, where memory +// resources are very limited, hence there are virtually no run-time checks +// present in the driver code. The objective is to keep the footprint as small +// as possible. For example, we do not keep a mirror image of palette. The con- +// sequence being that writing a palette entry and then reading it back may +// result in different value, as most of the supported chips don't support +// full 8 bits per primary colors (red,green,blue). +// This does not seem to affect the driver much. +// +// During the driver compilation, the following hash-defines are being used to +// identify the target Epson controller: +// +// CONFIG_FB_EPSON_S1D13504 +// CONFIG_FB_EPSON_S1D13505 +// CONFIG_FB_EPSON_S1D13506 +// CONFIG_FB_EPSON_S1D13704 +// CONFIG_FB_EPSON_S1D13705 +// CONFIG_FB_EPSON_S1D13706 +// CONFIG_FB_EPSON_S1D13806 +// CONFIG_FB_EPSON_S1D13A03 +// +// Most of the chips were tested using Epson evaluation boards. The boards come +// basically in two flavors: ISA bus adapters or PCI adapters. To support the +// PCI adapters, make sure to specify PCI bridge adapter during configuration. +// This will generate the following hash-define: +// +// CONFIG_FB_EPSON_PCI +// +// Additionally,there are some hash-defines specifying the display geometry +// and LUT register accesses. These are chip dependent and are located in +// corresponding S1D13XXX header files. +// +//----------------------------------------------------------------------------- + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +//----------------------------------------------------------------------------- +// +// Sanity checks +// +//----------------------------------------------------------------------------- + +// Check if at least one supported colordepth was configured + +// S1D13504 supports only 4Bpp,16Bpp, no PCI bridge card. +#ifdef CONFIG_FB_EPSON_S1D13504 + #if defined (CONFIG_FB_EPSON_PCI) + #error Invalid configuration! + #endif +#include "s1d13504.h" +#endif + +// S1D13505 supports 8Bpp,16Bpp, no PCI bridge card. +#ifdef CONFIG_FB_EPSON_S1D13505 + #if defined (CONFIG_FB_EPSON_PCI) + #error Invalid configuration! + #endif +#include "s1d13505.h" +#endif + +// S1D13506 supports 4Bpp,8Bpp,16Bpp +#ifdef CONFIG_FB_EPSON_S1D13506 +#include "s1d13506.h" +#endif + +// S1D13704 supports 4Bpp, no PCI bridge card +#ifdef CONFIG_FB_EPSON_S1D13704 + #if defined (CONFIG_FB_EPSON_PCI) + #error Invalid configuration! + #endif +#include "s1d13704.h" +#endif + +// S1D13705 supports 4Bpp, 8Bpp. No PCI bridge card +#ifdef CONFIG_FB_EPSON_S1D13705 + #if defined (CONFIG_FB_EPSON_PCI) + #error Invalid configuration! + #endif +#include "s1d13705.h" +#endif + +// S1D13706 supports 4Bpp, 8Bpp, 16Bpp +#ifdef CONFIG_FB_EPSON_S1D13706 +#include "s1d13706.h" +#endif + +// S1D13806 supports 4Bpp,8Bpp,16Bpp +#ifdef CONFIG_FB_EPSON_S1D13806 +#include "s1d13806.h" +#endif + +// S1D13A03 supports 4Bpp, 8Bpp, 16Bpp +#ifdef CONFIG_FB_EPSON_S1D13A03 +#include "s1d13a03.h" +#endif + +//----------------------------------------------------------------------------- +// +// Function Prototypes +// +//----------------------------------------------------------------------------- + +int __init s1d13xxxfb_setup(char *options); +int __init s1d13xxxfb_init(void); +void __init s1d13xxxdelayms(int ms); + +static int s1d13xxxfb_open(struct fb_info *info, int user); +static int s1d13xxxfb_release(struct fb_info *info, int user); + +static int s1d13xxx_encode_fix(struct fb_fix_screeninfo *fix, struct fb_var_screeninfo *var); +static int s1d13xxx_check_var(struct fb_var_screeninfo *var, struct fb_info *info); +static int s1d13xxx_encode_var(struct fb_var_screeninfo *var); +static int s1d13xxx_set_par(struct fb_info *info); +static void s1d13xxx_set_reg(struct fb_info *info, S1D_REGS aS1DRegs[], int size); +static int s1d13xxx_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, struct fb_info *info); +static int s1d13xxx_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info); +static int s1d13xxx_blank(int blank_mode, struct fb_info *info); + +//----------------------------------------------------------------------------- +// +// Local globals +// +//----------------------------------------------------------------------------- + +static struct fb_ops s1d13xxxfb_ops = { + .owner = THIS_MODULE, + .fb_open = s1d13xxxfb_open, + .fb_release = s1d13xxxfb_release, + .fb_set_par = s1d13xxx_set_par, + .fb_check_var = s1d13xxx_check_var, + .fb_setcolreg = s1d13xxx_setcolreg, + .fb_pan_display = s1d13xxx_pan_display, + .fb_blank = s1d13xxx_blank, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_cursor = soft_cursor, +}; + +static struct fb_fix_screeninfo s1d13xxxfb_fix __initdata = { + .id = "s1d13xxx", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_PSEUDOCOLOR, + .smem_len = S1D_PHYSICAL_VMEM_SIZE, + .mmio_len = S1D_PHYSICAL_REG_SIZE, + .xpanstep = 0, + .ypanstep = 0, + .ywrapstep = 0, + .type_aux = 0, + .accel = FB_ACCEL_NONE, +}; + +static struct fb_info fb_info; +static u32 pseudo_palette[17]; + +static char *mode_option __initdata = NULL; +static int lcd __initdata = 1; +#if 0 +static int bpp __initdata = 16; +static int xres __initdata = S1D_DISPLAY_WIDTH; +static int yres __initdata = S1D_DISPLAY_HEIGHT; +#endif + +//----------------------------------------------------------------------------- +// +// This function should fill in the 'fix' structure based on the values +// in the `par' structure. +// +//----------------------------------------------------------------------------- +static int s1d13xxx_encode_fix(struct fb_fix_screeninfo *fix, struct fb_var_screeninfo *var) +{ + /* set fix->line_length to the length of the line in bytes */ + fix->line_length = (var->xres * (var->bits_per_pixel/8)); + + switch(var->bits_per_pixel){ + case 4: + fix->visual = FB_VISUAL_STATIC_PSEUDOCOLOR; + break; + case 8: + fix->visual = FB_VISUAL_PSEUDOCOLOR; + break; + case 16: + fix->visual = FB_VISUAL_TRUECOLOR; + break; + case 32: + fix->visual = FB_VISUAL_TRUECOLOR; + break; + } + +#ifdef CONFIG_FB_EPSON_PCI + /* Start and length of Memory Mapped I/O */ + fix->mmio_start = (char*)fb_info.PhysAddr; + fix->mmio_len = S1D_PHYSICAL_REG_SIZE; + + /* Start and length of frame buffer mem */ + fix->smem_start = (char*)(fb_info.PhysAddr+0x200000); + fix->smem_len = S1D_PHYSICAL_VMEM_SIZE; +#else + /* Start and length of Memory Mapped I/O */ + fix->mmio_start = (unsigned long) + ioremap_nocache(S1D_PHYSICAL_REG_ADDR,S1D_PHYSICAL_REG_SIZE); + + /* Start and length of frame buffer mem */ + fix->smem_start = (unsigned long) + ioremap_nocache(S1D_PHYSICAL_VMEM_ADDR,S1D_PHYSICAL_VMEM_SIZE); +#endif + + return 0; +} + +//----------------------------------------------------------------------------- +// +// Fill the 'var' structure based on the values in 'par' and maybe other +// values read out of the hardware. +// +//----------------------------------------------------------------------------- + +static int s1d13xxx_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + return 0; +} + +static int s1d13xxx_encode_var(struct fb_var_screeninfo *var) +{ + var->grayscale = 0; + var->nonstd = 0; /* != 0 Non standard pixel format */ + var->activate = FB_ACTIVATE_NOW; /* see FB_ACTIVATE_* */ + var->height = -1; /* height of picture in mm */ + var->width = -1; /* width of picture in mm */ + var->accel_flags = 0; /* acceleration flags (hints) */ + + switch(var->bits_per_pixel){ + case 2: + case 4: + case 8: + var->red.offset = 0; + var->red.length = var->bits_per_pixel; + var->green.offset = 0; + var->green.length = var->bits_per_pixel; + var->blue.offset = 0; + var->blue.length = var->bits_per_pixel; + break; + case 16: /* RGB 565 */ + var->red.offset = 11; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 6; + var->blue.offset = 0; + var->blue.length = 5; + break; + case 32: + var->red.offset = 16; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + break; + } + + var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0; + var->transp.offset = var->transp.length = var->transp.msb_right = 0; + + return 0; +} + +//----------------------------------------------------------------------------- +// +// Set the hardware according to 'par'. +// +//----------------------------------------------------------------------------- +static int s1d13xxx_set_par(struct fb_info *info) +{ + return 0; +} + +static void s1d13xxx_set_reg(struct fb_info *info, S1D_REGS aS1DRegs[], int size) +{ + int i; + S1D_INDEX s1dReg; + S1D_VALUE s1dValue; + + + /* color depth independent value */ + for (i = 0; i < size; i++) + { + s1dReg = aS1DRegs[i].Index; + s1dValue = aS1DRegs[i].Value; + + if (s1dReg == S1D_REGDELAYOFF || s1dReg == S1D_REGDELAYON) + s1d13xxxdelayms((int)s1dValue); + else + { +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + /* swap register address */ + s1dReg = ((s1dReg & 1) ? (s1dReg & ~1L) : (s1dReg + 1)); +#endif + ((S1D_VALUE*)info->fix.mmio_start)[s1dReg/sizeof(S1D_VALUE)] = s1dValue; + } + } +} + +//---------------------------------------------------------------------------- +// +// Set a single color register. The values supplied have a 16 bit +// magnitude. +// Return != 0 for invalid regno. +// +// We get called even if we specified that we don't have a programmable palette +// or in direct/true color modes! +//---------------------------------------------------------------------------- +static int s1d13xxx_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, struct fb_info *info) +{ +// printk("S1D13XXX: (setcolreg) i:%d r=%x g=%x b=%x\n", regno,red,green,blue); + + if (regno >= S1D_PALETTE_SIZE) + return 1; + + S1D_WRITE_PALETTE(fb_info.fix.mmio_start,regno,red>>8,green>>8,blue>>8); + + if (info->var.grayscale) { + /* grayscale = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; + } + +#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + case FB_VISUAL_PSEUDOCOLOR: + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + break; + case FB_VISUAL_DIRECTCOLOR: + /* example here assumes 8 bit DAC. Might be different + * for your hardware */ + red = CNVT_TOHW(red, 8); + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + /* hey, there is bug in transp handling... */ + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + /* Truecolor has hardware independent palette */ + if (info->fix.visual == FB_VISUAL_TRUECOLOR) { + u32 v; + + if (regno >= 16) + return 1; + + v = (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + +#if 0 + switch (info->var.bits_per_pixel) { + case 8: + /* Yes some hand held devices have this. */ + ((u8*)(info->pseudo_palette))[regno] = v; + break; + case 16: + ((u16*)(info->pseudo_palette))[regno] = v; + break; + case 24: + case 32: + ((u32*)(info->pseudo_palette))[regno] = v; + break; + } +#endif + +#if defined(CONFIG_PLAT_MAPPI) + ((u32*)(info->pseudo_palette))[regno] = cpu_to_le32(v); +#else + ((u32*)(info->pseudo_palette))[regno] = v; +#endif + } + return 0; +} + +//----------------------------------------------------------------------------- +// +// Pan (or wrap, depending on the `vmode' field) the display using the +// `xoffset' and `yoffset' fields of the `var' structure. +// If the values don't fit, return -EINVAL. +// +//----------------------------------------------------------------------------- +static int s1d13xxx_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + return 0; +} + +//----------------------------------------------------------------------------- +// +// Blank the screen if blank_mode != 0, else unblank. If blank == NULL +// then the caller blanks by setting the CLUT (Color Look Up Table) to all +// black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due +// to e.g. a video mode which doesn't support it. Implements VESA suspend +// and powerdown modes on hardware that supports disabling hsync/vsync: +// +// 0 = unblank +// 1 = blank +// 2 = suspend vsync +// 3 = suspend hsync +// 4 = off +// +//----------------------------------------------------------------------------- +static int s1d13xxx_blank(int blank_mode, struct fb_info *info) +{ + return 0; +} + +//----------------------------------------------------------------------------- +// +// Detect our PCI bridge adapter card, get the BAR[0]. Card is assumed to be +// enabled. +// +//----------------------------------------------------------------------------- +#ifdef CONFIG_FB_EPSON_PCI +static int __init s1d13xxx_IsOurID(unsigned vID, unsigned dID) +{ + if (vID == 0x10F4 && dID == 0x1300) + return 1; + + if (vID == 0x14EB) + { + if (dID >= 0x0000 && dID < 0x002A) + return 1; + if (dID > 0x002A && dID <= 0x002F) + return 1; + } + return 0; +} + +unsigned long __init s1d13xxx_get_physical_address(void) +{ + struct pci_dev *pdev; + + pdev = NULL; + for (pdev = pci_devices; pdev != 0; pdev = pdev->next) + { + if (s1d13xxx_IsOurID(pdev->vendor,pdev->device)) + return (pdev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK); + } + return 0; +} +#endif + +void __init s1d13xxxdelayms(int ms) +{ + int i; + for (i = 0; i < ms; i++) + { + udelay(1000); + } +} + +//----------------------------------------------------------------------------- +// +// Initialize the chip and the frame buffer driver. +// +//----------------------------------------------------------------------------- +int __init s1d13xxxfb_init(void) +{ + int retval; + + if (!mode_option) + mode_option=DEFAULT_MODE; + + fb_info.fbops = &s1d13xxxfb_ops; + retval = fb_find_mode(&fb_info.var, &fb_info, mode_option, m32r_modedb, + sizeof(m32r_modedb)/sizeof(*m32r_modedb), NULL, 16); + + if (!retval || retval == 4) + return -EINVAL; + + fb_info.fix=s1d13xxxfb_fix; + s1d13xxx_encode_var(&fb_info.var); + s1d13xxx_encode_fix(&fb_info.fix,&fb_info.var); + + if (!fb_info.fix.mmio_start || !fb_info.fix.smem_start) + { + printk("s1d13xxx_init: ioremap() returned NULL\n"); + return 0; + } + + s1d13xxx_set_reg(&fb_info, aS1DRegs_common, + sizeof(aS1DRegs_common)/sizeof(aS1DRegs_common[0])); + switch (fb_info.var.bits_per_pixel) { + case 4: + s1d13xxx_set_reg(&fb_info, aS1DRegs_4bpp, + sizeof(aS1DRegs_4bpp)/sizeof(aS1DRegs_4bpp[0])); + break; + case 8: + s1d13xxx_set_reg(&fb_info, aS1DRegs_8bpp, + sizeof(aS1DRegs_8bpp)/sizeof(aS1DRegs_8bpp[0])); + break; + case 16: + s1d13xxx_set_reg(&fb_info, aS1DRegs_16bpp, + sizeof(aS1DRegs_16bpp)/sizeof(aS1DRegs_16bpp[0])); + break; + } + +#if defined(CONFIG_PLAT_MAPPI) + ((S1D_VALUE*)fb_info.fix.mmio_start)[0x01fc/sizeof(S1D_VALUE)] = lcd; +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) + ((S1D_VALUE*)fb_info.fix.mmio_start)[0x01fd/sizeof(S1D_VALUE)] = lcd; +#else +#error no platform configuration +#endif + + fb_info.node = -1; + fb_info.flags = FBINFO_FLAG_DEFAULT; + fb_info.screen_base = (void *)fb_info.fix.smem_start; + fb_info.pseudo_palette = pseudo_palette; + + fb_alloc_cmap(&fb_info.cmap, 256, 0); + + if (register_framebuffer(&fb_info) < 0) + return -EINVAL; + + printk(KERN_INFO "fb%d: %s frame buffer device\n", fb_info.node, + fb_info.fix.id); + + printk("Display %d x %d %dBpp\n", fb_info.var.xres, + fb_info.var.yres, fb_info.var.bits_per_pixel); + + return 0; +} + +//----------------------------------------------------------------------------- +// +// Parse user speficied options (`video=s1d13xxxfb:') +// +//----------------------------------------------------------------------------- +int __init s1d13xxxfb_setup(char *options) +{ + char *this_opt; + + if (!options || !*options) + return 0; + + while ((this_opt = strsep(&options, ",")) != NULL) { + if (!strncmp(this_opt, "lcd", 3)) + lcd = 1; + else if (!strncmp(this_opt, "crt", 3)) + lcd = 2; +#if 0 + else if (!strncmp(this_opt, "xres:", 5)) + xres = simple_strtoul(this_opt+5, NULL, 0); + else if (!strncmp(this_opt, "yres:", 5)) + yres = simple_strtoul(this_opt+5, NULL, 0); + else if (!strncmp(this_opt, "bpp:", 4)) + bpp = simple_strtoul(this_opt+4, NULL, 0); +#endif + else if (!strncmp(this_opt, "mode:", 5)) + mode_option = this_opt+5; + } + + return 0; +} + +/* ------------------------------------------------------------------------- */ +static int s1d13xxxfb_open(struct fb_info *info, int user) +{ + /* Nothing, only a usage count for the moment */ + MOD_INC_USE_COUNT; + return 0; +} + +static int s1d13xxxfb_release(struct fb_info *info, int user) +{ + MOD_DEC_USE_COUNT; + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* + * Modularization + */ + +#ifdef MODULE +int init_module(void) +{ + s1d13xxxfb_init(); + return 0; +} + +void cleanup_module(void) +{ + unregister_framebuffer(&fb_info); +} +#endif /* MODULE */ + diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/fs/proc/base.c linux-2.6.8.1/fs/proc/base.c --- linux-2.6.8.1.org/fs/proc/base.c 2004-08-14 19:55:35.000000000 +0900 +++ linux-2.6.8.1/fs/proc/base.c 2004-08-30 10:24:04.000000000 +0900 @@ -449,7 +449,7 @@ return -EACCES; return proc_check_root(inode); } - +#ifdef CONFIG_MMU extern struct seq_operations proc_pid_maps_op; static int maps_open(struct inode *inode, struct file *file) { @@ -468,6 +468,7 @@ .llseek = seq_lseek, .release = seq_release, }; +#endif /* CONFIG_MMU */ extern struct seq_operations mounts_op; static int mounts_open(struct inode *inode, struct file *file) @@ -1333,10 +1334,12 @@ inode->i_fop = &proc_info_file_operations; ei->op.proc_read = proc_pid_statm; break; +#ifdef CONFIG_MMU case PROC_TID_MAPS: case PROC_TGID_MAPS: inode->i_fop = &proc_maps_operations; break; +#endif case PROC_TID_MEM: case PROC_TGID_MEM: inode->i_op = &proc_mem_inode_operations; diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/include/linux/elf.h linux-2.6.8.1/include/linux/elf.h --- linux-2.6.8.1.org/include/linux/elf.h 2004-08-14 19:54:50.000000000 +0900 +++ linux-2.6.8.1/include/linux/elf.h 2004-08-30 10:24:14.000000000 +0900 @@ -87,6 +87,7 @@ #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ #define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Renesas M32R */ #define EM_H8_300 46 /* Hitachi H8/300,300H,H8S */ @@ -95,6 +96,7 @@ * up with a final number. */ #define EM_ALPHA 0x9026 +#define EM_CYGNUS_M32R 0x9041 /* Bogus old v850 magic number, used by old tools. */ #define EM_CYGNUS_V850 0x9080 diff -ruN -xasm-m32r -xm32r linux-2.6.8.1.org/include/linux/videodev.h linux-2.6.8.1/include/linux/videodev.h --- linux-2.6.8.1.org/include/linux/videodev.h 2004-08-14 19:56:25.000000000 +0900 +++ linux-2.6.8.1/include/linux/videodev.h 2004-08-30 10:24:14.000000000 +0900 @@ -432,6 +432,7 @@ #define VID_HARDWARE_W9968CF 36 #define VID_HARDWARE_SAA7114H 37 #define VID_HARDWARE_SN9C102 38 +#define VID_HARDWARE_ARV 39 #endif /* __LINUX_VIDEODEV_H */ /*