diff -Naur linux-2.6.14.6-20060127.org/arch/m32r/kernel/io_m32700ut.c linux-2.6.14.6-20060127/arch/m32r/kernel/io_m32700ut.c --- linux-2.6.14.6-20060127.org/arch/m32r/kernel/io_m32700ut.c 2006-01-27 19:00:31.000000000 +0900 +++ linux-2.6.14.6-20060127/arch/m32r/kernel/io_m32700ut.c 2006-03-20 09:28:39.000000000 +0900 @@ -4,7 +4,8 @@ * Typical I/O routines for M32700UT board. * * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, - * Hitoshi Yamamoto, Takeo Takahashi + * Hitoshi Yamamoto, Takeo Takahashi, + * Hayato Fujiwara * * This file is subject to the terms and conditions of the GNU General * Public License. See the file "COPYING" in the main directory of this @@ -32,11 +33,10 @@ #endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */ #define PORT2ADDR(port) _port2addr(port) -#define PORT2ADDR_USB(port) _port2addr_usb(port) static inline void *_port2addr(unsigned long port) { - return (void *)(port | NONCACHE_OFFSET); + return (void *)(port | (NONCACHE_OFFSET)); } #if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC) @@ -70,10 +70,6 @@ { return (void *)(port + 0x10000000); } -static inline void *_port2addr_usb(unsigned long port) -{ - return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000); -} static inline void delay(void) { @@ -144,10 +140,6 @@ return *(volatile unsigned short *)__port2addr_ata(port); } #endif -#if defined(CONFIG_USB) - else if(port >= 0x340 && port < 0x3a0) - return *(volatile unsigned short *)PORT2ADDR_USB(port); -#endif #if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC) else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) { unsigned short w; @@ -219,11 +211,6 @@ *(volatile unsigned short *)__port2addr_ata(port) = w; } else #endif -#if defined(CONFIG_USB) - if(port >= 0x340 && port < 0x3a0) - *(volatile unsigned short *)PORT2ADDR_USB(port) = w; - else -#endif #if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC) if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) { pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0); diff -Naur linux-2.6.14.6-20060127.org/arch/m32r/kernel/setup_m32700ut.c linux-2.6.14.6-20060127/arch/m32r/kernel/setup_m32700ut.c --- linux-2.6.14.6-20060127.org/arch/m32r/kernel/setup_m32700ut.c 2006-01-27 19:00:31.000000000 +0900 +++ linux-2.6.14.6-20060127/arch/m32r/kernel/setup_m32700ut.c 2006-04-11 09:26:15.000000000 +0900 @@ -4,7 +4,8 @@ * Setup routines for Renesas M32700UT Board * * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata, - * Hitoshi Yamamoto, Takeo Takahashi + * Hitoshi Yamamoto, Takeo Takahashi, + * Hayato Fujiwara * * This file is subject to the terms and conditions of the GNU General * Public License. See the file "COPYING" in the main directory of this @@ -235,8 +236,16 @@ * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2) */ #define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE) -#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \ - (((x) - 1) * sizeof(unsigned short))) + +static __inline__ unsigned long lcdpldirq2port(unsigned int irq) +{ + if (irq < 5) { + return (unsigned long)((int)M32700UT_LCD_ICUCR1 + + ((irq - 1) * sizeof(unsigned short))); + } + return (unsigned long)((int)M32700UT_LCD_ICUCR16 + + ((irq - 16) * sizeof(unsigned short))); +} static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ]; @@ -419,12 +428,12 @@ #if defined(CONFIG_USB) outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ - irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; - irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; - lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ - disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); + irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; + irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type; + irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; + irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; + lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ + disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); #endif #if defined(CONFIG_M32700UT_TS) @@ -435,6 +444,14 @@ lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_BAT_INT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; /* "H" level sense */ disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_BAT_INT); #endif + /* INT2 : SOUND data interrupt */ + irq_desc[M32700UT_LCD_IRQ_ASNDSIO_SND].status = IRQ_DISABLED; + irq_desc[M32700UT_LCD_IRQ_ASNDSIO_SND].handler = &m32700ut_lcdpld_irq_type; + irq_desc[M32700UT_LCD_IRQ_ASNDSIO_SND].action = 0; + irq_desc[M32700UT_LCD_IRQ_ASNDSIO_SND].depth = 1; + lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_ASNDSIO_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; /* "L" level sense */ + disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_ASNDSIO_SND); + /* * INT2# is used for BAT, USB, AUDIO * We enable it here. @@ -519,6 +536,64 @@ }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) + +#include +#include + +static void isp1362_delay(struct device *dev, unsigned int delay) +{ + ndelay(delay * 2); +} + +static struct isp1362_platform_data isp1362_hcd_data = { + .reset = NULL, + .delay = isp1362_delay, + .clock = NULL, + .potpg = 25, + .no_power_switching = 1, + .power_switching_mode = 0, + .remote_wakeup_connected = 1, + .int_edge_triggered = 0, + .int_act_high = 0, + .dreq_act_high = 1, + .dack_act_high = 0, + .oc_enable = 0, + .sel15Kres = 0, +}; + +static struct resource isp1362_hcd_resources[] = { + [0] = { + .name = "isp1362-hcd data reg", + .start = 0x10303000UL, + .end = 0x10303001UL, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "isp1362-hcd addr reg", + .start = 0x10303002UL, + .end = 0x10303003UL, + .flags = IORESOURCE_MEM, + }, + [2] = { + .name = "isp1362-hcd irq", + .start = M32700UT_LCD_IRQ_USB_INT1, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device isp1362_device = { + .name = "isp1362-hcd", + .id = 0, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, + .dev = { + .platform_data = &isp1362_hcd_data, + } +}; + +#endif + static int __init platform_init(void) { #if defined(CONFIG_SMC91X) @@ -527,6 +602,10 @@ #if defined(CONFIG_FB_S1D13XXX) platform_device_register(&s1d13xxxfb_device); #endif +#if defined(CONFIG_USB_ISP1362_HCD) + outw(USBCR_OTGS|USBCR_HSWS, USBCR); + platform_device_register(&isp1362_device); +#endif return 0; } arch_initcall(platform_init); diff -Naur linux-2.6.14.6-20060127.org/drivers/media/video/arv.c linux-2.6.14.6-20060127/drivers/media/video/arv.c --- linux-2.6.14.6-20060127.org/drivers/media/video/arv.c 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/media/video/arv.c 2006-04-14 14:49:07.000000000 +0900 @@ -391,7 +391,7 @@ ret = -EFAULT; goto out_up; } - DEBUG(1, "ret = %d\n", ret); + DEBUG(1, "ret = %ld\n", ret); out_up: up(&ar->lock); return ret; diff -Naur linux-2.6.14.6-20060127.org/drivers/usb/Kconfig linux-2.6.14.6-20060127/drivers/usb/Kconfig --- linux-2.6.14.6-20060127.org/drivers/usb/Kconfig 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/usb/Kconfig 2006-03-20 09:38:15.000000000 +0900 @@ -27,6 +27,11 @@ default y if PPC_MPC52xx # MIPS: default y if SOC_AU1X00 + # M32R + default y if PLAT_M32700UT + default y if PLAT_OPSPUT + default y if PLAT_MAPPI2 + default y if PLAT_MAPPI3 # more: default PCI diff -Naur linux-2.6.14.6-20060127.org/drivers/usb/Makefile linux-2.6.14.6-20060127/drivers/usb/Makefile --- linux-2.6.14.6-20060127.org/drivers/usb/Makefile 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/usb/Makefile 2006-03-20 09:42:49.000000000 +0900 @@ -10,6 +10,7 @@ obj-$(CONFIG_USB_EHCI_HCD) += host/ obj-$(CONFIG_USB_ISP116X_HCD) += host/ +obj-$(CONFIG_USB_ISP1362_HCD) += host/ obj-$(CONFIG_USB_OHCI_HCD) += host/ obj-$(CONFIG_USB_UHCI_HCD) += host/ obj-$(CONFIG_USB_SL811_HCD) += host/ diff -Naur linux-2.6.14.6-20060127.org/drivers/usb/host/Kconfig linux-2.6.14.6-20060127/drivers/usb/host/Kconfig --- linux-2.6.14.6-20060127.org/drivers/usb/host/Kconfig 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/usb/host/Kconfig 2006-03-20 09:46:15.000000000 +0900 @@ -62,6 +62,18 @@ To compile this driver as a module, choose M here: the module will be called isp116x-hcd. +config USB_ISP1362_HCD + tristate "ISP1362 HCD support" + depends on USB + default N + ---help--- + Supports the Philips ISP1362 chip as a host controller + + This driver does not support isochronous transfers. + + To compile this driver as a module, choose M here: the + module will be called isp1362-hcd. + config USB_OHCI_HCD tristate "OHCI HCD support" depends on USB && USB_ARCH_HAS_OHCI diff -Naur linux-2.6.14.6-20060127.org/drivers/usb/host/Makefile linux-2.6.14.6-20060127/drivers/usb/host/Makefile --- linux-2.6.14.6-20060127.org/drivers/usb/host/Makefile 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/usb/host/Makefile 2006-03-20 09:46:33.000000000 +0900 @@ -5,6 +5,7 @@ obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o +obj-$(CONFIG_USB_ISP1362_HCD) += isp1362-hcd.o obj-$(CONFIG_USB_OHCI_HCD) += ohci-hcd.o obj-$(CONFIG_USB_UHCI_HCD) += uhci-hcd.o obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o diff -Naur linux-2.6.14.6-20060127.org/drivers/usb/host/isp1362-hcd.c linux-2.6.14.6-20060127/drivers/usb/host/isp1362-hcd.c --- linux-2.6.14.6-20060127.org/drivers/usb/host/isp1362-hcd.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/usb/host/isp1362-hcd.c 2006-04-13 17:41:44.000000000 +0900 @@ -0,0 +1,3125 @@ +/* + * ISP1362 HCD (Host Controller Driver) for USB. + * + * Copyright (C) 2005 Lothar Wassmann + * + * Derived from the SL811 HCD, rewritten for ISP116x. + * Copyright (C) 2005 Olav Kongas + * + * Portions: + * Copyright (C) 2004 Psion Teklogix (for NetBook PRO) + * Copyright (C) 2004 David Brownell + * Copyright (C) 2005 Hayato Fujiwara (for M32R) + * + */ + +/* + The ISP1362 chip requires a large delay (300ns and 462ns) between + accesses to the address and data register. + The following timing options exist: + + 1. Configure your memory controller if it can accommodate such delays (the best) + 2. Implement platform-specific delay function possibly + combined with configuring the memory controller; see + include/linux/usb_isp1362.h for more info. + 3. Use ndelay (easiest, poorest). + + Use the corresponding macros USE_PLATFORM_DELAY and USE_NDELAY in the + platform specific section of isp1362.h to select the appropriate variant. + + Also note that according to the Philips "ISP1362 Errata" document + Rev 1.00 from 27 May data corruption may occur when the #WR signal + is reasserted (even with #CS deasserted) within 132ns after a + write cycle to any controller register. If the hardware doesn't + implement the recommended fix (gating the #WR with #CS) software + must ensure that no further write cycle (not necessarily to the chip!) + is issued by the CPU within this interval. + + For PXA25x this can be ensured by using VLIO with the maximum + recovery time (MSCx = 0x7f8c) with a memory clock of 99.53 MHz. +*/ + +#include + +#ifdef CONFIG_USB_DEBUG +# define DEBUG +#else +# undef DEBUG +#endif + +/* + * The PXA255 UDC apparently doesn't handle GET_STATUS, GET_CONFIG and + * GET_INTERFACE requests correctly when the SETUP and DATA stages of the + * requests are carried out in separate frames. This will delay any SETUP + * packets until the start of the next frame so that this situation is + * unlikely to occur (and makes usbtest happy running with a PXA255 target device). + */ +// #define BUGGY_PXA2XX_UDC_USBTEST + +#undef PTD_TRACE +#undef URB_TRACE +#undef VERBOSE +#undef REGISTERS + +/* This enables a memory test on the ISP1362 chip memory to make sure the + * chip access timing is correct. + */ +// #define CHIP_BUFFER_TEST + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static int dbg_level = 0; +#ifdef DEBUG +module_param(dbg_level, int, 0644); +#else +module_param(dbg_level, int, 0); +#define STUB_DEBUG_FILE +#endif + +#include "../core/hcd.h" +#include "isp1362.h" + + +#define DRIVER_VERSION "2005-04-04" +#define DRIVER_DESC "ISP1362 USB Host Controller Driver" + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); + +static const char hcd_name[] = "isp1362-hcd"; + +static void isp1362_hc_stop(struct usb_hcd *hcd); +static int isp1362_hc_start(struct usb_hcd *hcd); + +/*-------------------------------------------------------------------------*/ + +/* + * When called from the interrupthandler only isp1362_hcd->irqenb is modified, + * since the interrupt handler will write isp1362_hcd->irqenb to HCuPINT upon + * completion. + * We don't need a 'disable' counterpart, since interrupts will be disabled + * only by the interrupt handler. + */ +static inline void isp1362_enable_int(struct isp1362_hcd *isp1362_hcd, u16 mask) +{ + if ((isp1362_hcd->irqenb | mask) == isp1362_hcd->irqenb) { + return; + } + if (mask & ~isp1362_hcd->irqenb) { + isp1362_write_reg16(isp1362_hcd, HCuPINT, mask & ~isp1362_hcd->irqenb); + } + isp1362_hcd->irqenb |= mask; + if (isp1362_hcd->irq_active) { + return; + } + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, isp1362_hcd->irqenb); +} + +/*-------------------------------------------------------------------------*/ + +static inline struct isp1362_ep_queue *get_ptd_queue(struct isp1362_hcd *isp1362_hcd, + u16 offset) +{ + struct isp1362_ep_queue * epq = NULL; + + if (offset < isp1362_hcd->istl_queue[1].buf_start) { + epq = &isp1362_hcd->istl_queue[0]; + } else if (offset < isp1362_hcd->intl_queue.buf_start) { + epq = &isp1362_hcd->istl_queue[1]; + } else if (offset < isp1362_hcd->atl_queue.buf_start) { + epq = &isp1362_hcd->intl_queue; + } else if (offset < isp1362_hcd->atl_queue.buf_start + + isp1362_hcd->atl_queue.buf_size) { + epq = &isp1362_hcd->atl_queue; + } + if (epq) { + DBG(1, "%s: PTD $%04x is on %s queue\n", __FUNCTION__, offset, epq->name); + } else { + WARN("%s: invalid PTD $%04x\n", __FUNCTION__, offset); + } + + return epq; +} + +static inline int get_ptd_offset(struct isp1362_ep_queue *epq, u8 index) +{ + int offset; + + if (index * epq->blk_size > epq->buf_size) { + WARN("%s: Bad %s index %d(%d)\n", __FUNCTION__, epq->name, index, + epq->buf_size / epq->blk_size); + return -EINVAL; + } + offset = epq->buf_start + index * epq->blk_size; + DBG(3, "%s: %s PTD[%02x] # %04x\n", __FUNCTION__, epq->name, index, offset); + + return offset; +} + +/*-------------------------------------------------------------------------*/ + +static inline u16 max_transfer_size(struct isp1362_ep_queue *epq, size_t size, int mps) +{ + u16 xfer_size = min_t(size_t, MAX_XFER_SIZE, size); + + xfer_size = min_t(size_t, xfer_size, epq->buf_avail * epq->blk_size - PTD_HEADER_SIZE); + if (xfer_size < size && xfer_size % mps) { + xfer_size -= xfer_size % mps; + } + + return xfer_size; +} + +static int claim_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1362_ep *ep, u16 len) +{ + int ptd_offset = -EINVAL; + int index; + int num_ptds = ((len + PTD_HEADER_SIZE - 1) / epq->blk_size) + 1; + int found = -1; + int last = -1; + + BUG_ON(len > epq->buf_size); + + if (!epq->buf_avail) { + return -ENOMEM; + } + + if (ep->num_ptds) { + ERR("%s: %s len %d/%d num_ptds %d buf_map %08lx skip_map %08lx\n", __FUNCTION__, + epq->name, len, epq->blk_size, num_ptds, epq->buf_map, epq->skip_map); + } + BUG_ON(ep->num_ptds != 0); + + for (index = 0; index <= epq->buf_count - num_ptds; index++) { + if (test_bit(index, &epq->buf_map)) { + continue; + } + found = index; + for (last = index + 1; last < index + num_ptds; last++) { + if (test_bit(last, &epq->buf_map)) { + found = -1; + break; + } + } + if (found >= 0) { + break; + } + } + if (found < 0) { + return -EOVERFLOW; + } + + DBG(1, "%s: Found %d PTDs[%d] for %d/%d byte\n", __FUNCTION__, + num_ptds, found, len, epq->blk_size - PTD_HEADER_SIZE); + ptd_offset = get_ptd_offset(epq, found); + WARN_ON(ptd_offset < 0); + ep->ptd_offset = ptd_offset; + ep->num_ptds += num_ptds; + epq->buf_avail -= num_ptds; + BUG_ON(epq->buf_avail > epq->buf_count); + ep->ptd_index = found; + for (index = found; index < last; index++) { + __set_bit(index, &epq->buf_map); + } + DBG(1, "%s: Done %s PTD[%d] $%04x, avail %d count %d claimed %d %08lx:%08lx\n", + __FUNCTION__, epq->name, ep->ptd_index, ep->ptd_offset, + epq->buf_avail, epq->buf_count, num_ptds, epq->buf_map, epq->skip_map); + + return found; +} + +static inline void release_ptd_buffers(struct isp1362_ep_queue *epq, struct isp1362_ep *ep) +{ + int index = ep->ptd_index; + int last = ep->ptd_index + ep->num_ptds; + + if (last > epq->buf_count) { + ERR("%s: ep %p req %d len %d %s PTD[%d] $%04x num_ptds %d buf_count %d buf_avail %d buf_map %08lx skip_map %08lx\n", + __FUNCTION__, ep, ep->num_req, ep->length, epq->name, ep->ptd_index, + ep->ptd_offset, ep->num_ptds, epq->buf_count, epq->buf_avail, + epq->buf_map, epq->skip_map); + } + BUG_ON(last > epq->buf_count); + + for (; index < last; index++) { + __clear_bit(index, &epq->buf_map); + __set_bit(index, &epq->skip_map); + } + epq->buf_avail += ep->num_ptds; + epq->ptd_count--; + + BUG_ON(epq->buf_avail > epq->buf_count); + BUG_ON(epq->ptd_count > epq->buf_count); + + DBG(1, "%s: Done %s PTDs $%04x released %d avail %d count %d\n", + __FUNCTION__, epq->name, + ep->ptd_offset, ep->num_ptds, epq->buf_avail, epq->buf_count); + DBG(1, "%s: buf_map %08lx skip_map %08lx\n", __FUNCTION__, + epq->buf_map, epq->skip_map); + + ep->num_ptds = 0; + ep->ptd_offset = -EINVAL; + ep->ptd_index = -EINVAL; +} + +/*-------------------------------------------------------------------------*/ + +/* + Set up PTD's. +*/ +static void prepare_ptd(struct isp1362_hcd *isp1362_hcd, struct urb *urb, struct isp1362_ep *ep, + struct isp1362_ep_queue *epq, u16 fno) +{ + struct ptd *ptd; + int toggle; + int dir; + u16 len; + size_t buf_len = urb->transfer_buffer_length - urb->actual_length; + + DBG(3, "%s: %s ep %p\n", __func__, epq->name, ep); + + ptd = &ep->ptd; + + spin_lock(&urb->lock); + ep->data = (unsigned char *)urb->transfer_buffer + urb->actual_length; + + switch (ep->nextpid) { + case USB_PID_IN: + toggle = usb_gettoggle(urb->dev, ep->epnum, 0); + dir = PTD_DIR_IN; + if (usb_pipecontrol(urb->pipe)) { + len = min_t(size_t, ep->maxpacket, buf_len); + } else if (usb_pipeisoc(urb->pipe)) { + len = min_t(size_t, urb->iso_frame_desc[fno].length, MAX_XFER_SIZE); + ep->data = urb->transfer_buffer + urb->iso_frame_desc[fno].offset; + } else { + len = max_transfer_size(epq, buf_len, ep->maxpacket); + } + DBG(1, "%s: IN len %d/%d/%d from URB\n", __FUNCTION__, len, ep->maxpacket, + buf_len); + break; + case USB_PID_OUT: + toggle = usb_gettoggle(urb->dev, ep->epnum, 1); + dir = PTD_DIR_OUT; + if (usb_pipecontrol(urb->pipe)) { + len = min_t(size_t, ep->maxpacket, buf_len); + } else if (usb_pipeisoc(urb->pipe)) { + len = min_t(size_t, urb->iso_frame_desc[0].length, MAX_XFER_SIZE); + } else { + len = max_transfer_size(epq, buf_len, ep->maxpacket); + } + if (len == 0) { + INFO("%s: Sending ZERO packet: %d\n", __FUNCTION__, + urb->transfer_flags & URB_ZERO_PACKET); + } + DBG(1, "%s: OUT len %d/%d/%d from URB\n", __FUNCTION__, len, ep->maxpacket, + buf_len); + break; + case USB_PID_SETUP: + toggle = 0; + dir = PTD_DIR_SETUP; + len = sizeof(struct usb_ctrlrequest); + DBG(1, "%s: SETUP len %d\n", __FUNCTION__, len); + ep->data = urb->setup_packet; + break; + case USB_PID_ACK: + toggle = 1; + len = 0; + dir = (urb->transfer_buffer_length && usb_pipein(urb->pipe)) ? + PTD_DIR_OUT : PTD_DIR_IN; + DBG(1, "%s: ACK len %d\n", __FUNCTION__, len); + break; + default: + // To please gcc + toggle = dir = len = 0; + ERR("%s@%d: ep->nextpid %02x\n", __func__, __LINE__, ep->nextpid); + BUG_ON(1); + } + + ep->length = len; + if (!len) { + ep->data = NULL; + } + + ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK | PTD_TOGGLE(toggle); + ptd->mps = PTD_MPS(ep->maxpacket) | PTD_SPD(urb->dev->speed == USB_SPEED_LOW) | + PTD_EP(ep->epnum); + ptd->len = PTD_LEN(len) | PTD_DIR(dir); + ptd->faddr = PTD_FA(usb_pipedevice(urb->pipe)); + + if (usb_pipeint(urb->pipe)) { + ptd->faddr |= PTD_SF_INT(ep->branch); + ptd->faddr |= PTD_PR(ep->interval ? __ffs(ep->interval) : 0); + } + if (usb_pipeisoc(urb->pipe)) { + ptd->faddr |= PTD_SF_ISO(fno); + } + + spin_unlock(&urb->lock); + DBG(1, "%s: Finished\n", __FUNCTION__); +} + +static void isp1362_write_ptd(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep *ep, + struct isp1362_ep_queue *epq) +{ + struct ptd *ptd = &ep->ptd; + int len = PTD_GET_DIR(ptd) == PTD_DIR_IN ? 0 : ep->length; + + _BUG_ON(ep->ptd_offset < 0); + + prefetch(ptd); + isp1362_write_buffer(isp1362_hcd, ptd, ep->ptd_offset, PTD_HEADER_SIZE, 0); + if (len) { + isp1362_write_buffer(isp1362_hcd, ep->data, + ep->ptd_offset + PTD_HEADER_SIZE, len, 1); + } + + dump_ptd(ptd); + dump_ptd_out_data(ptd, ep->data); +} + +static void isp1362_read_ptd(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep *ep, + struct isp1362_ep_queue *epq) +{ + struct ptd *ptd = &ep->ptd; + int act_len; + + WARN_ON(list_empty(&ep->active)); + BUG_ON(ep->ptd_offset < 0); + + list_del_init(&ep->active); + DBG(1, "%s: ep %p removed from active list %p\n", __FUNCTION__, ep, &epq->active); + + prefetchw(ptd); + isp1362_read_buffer(isp1362_hcd, ptd, ep->ptd_offset, PTD_HEADER_SIZE,0); + dump_ptd(ptd); + act_len = PTD_GET_COUNT(ptd); + if (PTD_GET_DIR(ptd) != PTD_DIR_IN || act_len == 0) { + return; + } + if (act_len > ep->length) { + ERR("%s: ep %p PTD $%04x act_len %d ep->length %d\n", __FUNCTION__, ep, + ep->ptd_offset, act_len, ep->length); + } + BUG_ON(act_len > ep->length); + /* Only transfer the amount of data that has actually been overwritten + * in the chip buffer. We don't want any data that doesn't belong to the + * transfer to leak out of the chip to the callers transfer buffer! + */ + prefetchw(ep->data); + isp1362_read_buffer(isp1362_hcd, ep->data, + ep->ptd_offset + PTD_HEADER_SIZE, act_len, 1); + dump_ptd_in_data(ptd, ep->data); +} + +/* + * INT PTDs will stay in the chip until data is available. + * This function will remove a PTD from the chip when the URB is dequeued. + * Must be called with the spinlock held and IRQs disabled + */ +static void remove_ptd(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep *ep) + +{ + int index; + struct isp1362_ep_queue *epq; + + DBG(1, "%s: ep %p PTD[%d] $%04x\n", __FUNCTION__, ep, ep->ptd_index, ep->ptd_offset); + BUG_ON(ep->ptd_offset < 0); + + epq = get_ptd_queue(isp1362_hcd, ep->ptd_offset); + BUG_ON(!epq); + + // put ep in remove_list for cleanup + WARN_ON(!list_empty(&ep->remove_list)); + list_add_tail(&ep->remove_list, &isp1362_hcd->remove_list); + // let SOF interrupt handle the cleanup + isp1362_enable_int(isp1362_hcd, HCuPINT_SOF); + + index = ep->ptd_index; + if (index < 0) { + // ISO queues don't have SKIP registers + return; + } + + DBG(1, "%s: Disabling PTD[%02x] $%04x %08lx|%08x\n", __FUNCTION__, + index, ep->ptd_offset, epq->skip_map, 1 << index); + + // prevent further processing of PTD (will be effective after next SOF) + epq->skip_map |= 1 << index; + if (epq == &isp1362_hcd->atl_queue) { + DBG(2, "%s: ATLSKIP = %08x -> %08lx\n", __FUNCTION__, + isp1362_read_reg32(isp1362_hcd, HCATLSKIP), epq->skip_map); + isp1362_write_reg32(isp1362_hcd, HCATLSKIP, epq->skip_map); + if (~epq->skip_map == 0) { + isp1362_clr_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_ATL_ACTIVE); + } + } else if (epq == &isp1362_hcd->intl_queue) { + DBG(2, "%s: INTLSKIP = %08x -> %08lx\n", __FUNCTION__, + isp1362_read_reg32(isp1362_hcd, HCINTLSKIP), epq->skip_map); + isp1362_write_reg32(isp1362_hcd, HCINTLSKIP, epq->skip_map); + if (~epq->skip_map == 0) { + isp1362_clr_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_INTL_ACTIVE); + } + } +} + +/* + Take done or failed requests out of schedule. Give back + processed urbs. +*/ +static void finish_request(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep *ep, + struct urb *urb, struct pt_regs *regs, int status) + __releases(isp1362_hcd->lock) + __acquires(isp1362_hcd->lock) +{ + urb->hcpriv = NULL; + ep->error_count = 0; + + if (usb_pipecontrol(urb->pipe)) { + ep->nextpid = USB_PID_SETUP; + } + + spin_lock(&urb->lock); + if (urb->status == -EINPROGRESS) { + urb->status = status; + } + spin_unlock(&urb->lock); + URB_DBG("%s: req %d FA %d ep%d%s %s: len %d/%d %s stat %d\n", __func__, + ep->num_req, usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), + !usb_pipein(urb->pipe) ? "out" : "in", + ({ + char *s; + if (usb_pipecontrol(urb->pipe)) { + s = "ctrl"; + } else if(usb_pipeint(urb->pipe)) { + s = "int"; + } else if(usb_pipebulk(urb->pipe)) { + s = "bulk"; + } else { + s = "iso"; + } + s;}), + urb->actual_length, urb->transfer_buffer_length, + !(urb->transfer_flags & URB_SHORT_NOT_OK) ? + "short_ok" : "", urb->status); + + spin_unlock(&isp1362_hcd->lock); + usb_hcd_giveback_urb(isp1362_hcd_to_hcd(isp1362_hcd), urb, regs); + spin_lock(&isp1362_hcd->lock); + + // take idle endpoints out of the schedule right away + if (!list_empty(&ep->hep->urb_list)) { + return; + } + + if (ep->interval) { + // periodic deschedule + DBG(1, "deschedule qh%d/%p branch %d load %d bandwidth %d -> %d\n", ep->interval, + ep, ep->branch, ep->load, + isp1362_hcd->load[ep->branch], + isp1362_hcd->load[ep->branch] - ep->load); + isp1362_hcd->load[ep->branch] -= ep->load; + ep->branch = PERIODIC_SIZE; + if (urb->bandwidth) { + DBG(0, "%s: Releasing bandwidth for urb %p ep %p req %d\n", + __FUNCTION__, urb, ep, ep->num_req); + usb_release_bandwidth(urb->dev, urb, usb_pipeisoc(urb->pipe)); + } + } + // async deschedule + if (!list_empty(&ep->schedule)) { + list_del_init(&ep->schedule); + } +} + +/* + * Analyze transfer results, handle partial transfers and errors +*/ +static void postproc_ep(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep *ep, + struct pt_regs *regs) +{ + struct urb *urb = get_urb(ep); + struct usb_device *udev; + struct ptd *ptd; + int short_ok; + u16 len; + int urbstat = -EINPROGRESS; + u8 cc; + + DBG(2, "%s: ep %p req %d\n", __FUNCTION__, ep, ep->num_req); + + udev = urb->dev; + ptd = &ep->ptd; + cc = PTD_GET_CC(ptd); + if (cc == PTD_NOTACCESSED) { + ERR("%s: req %d PTD %p Untouched by ISP1362\n", __FUNCTION__, + ep->num_req, ptd); + cc = PTD_DEVNOTRESP; + } + + short_ok = !(urb->transfer_flags & URB_SHORT_NOT_OK); + len = urb->transfer_buffer_length - urb->actual_length; + + /* Data underrun is special. For allowed underrun + we clear the error and continue as normal. For + forbidden underrun we finish the DATA stage + immediately while for control transfer, + we do a STATUS stage. + */ + if (cc == PTD_DATAUNDERRUN) { + if (short_ok) { + DBG(1, "%s: req %d Allowed data underrun short_%sok %d/%d/%d byte\n", + __func__, ep->num_req, short_ok ? "" : "not_", + PTD_GET_COUNT(ptd), ep->maxpacket, len); + cc = PTD_CC_NOERROR; + urbstat = 0; + } else { + DBG(1, "%s: req %d Data Underrun %s nextpid %02x short_%sok %d/%d/%d byte\n", + __FUNCTION__, ep->num_req, + usb_pipein(urb->pipe) ? "IN" : "OUT", ep->nextpid, + short_ok ? "" : "not_", + PTD_GET_COUNT(ptd), ep->maxpacket, len); + if (usb_pipecontrol(urb->pipe)) { + ep->nextpid = USB_PID_ACK; + // save the data underrun error code for later and + // procede with the status stage + urb->actual_length += PTD_GET_COUNT(ptd); + BUG_ON(urb->actual_length > urb->transfer_buffer_length); + spin_lock(&urb->lock); + if (urb->status == -EINPROGRESS) { + urb->status = cc_to_error[PTD_DATAUNDERRUN]; + } + spin_unlock(&urb->lock); + } else { + usb_settoggle(udev, ep->epnum, ep->nextpid == USB_PID_OUT, + PTD_GET_TOGGLE(ptd)); + urbstat = cc_to_error[PTD_DATAUNDERRUN]; + } + goto out; + } + } + + if (cc != PTD_CC_NOERROR) { + if (++ep->error_count >= 3 || cc == PTD_CC_STALL || cc == PTD_DATAOVERRUN) { + urbstat = cc_to_error[cc]; + DBG(1, "%s: req %d nextpid %02x, status %d, error %d, error_count %d\n", + __func__, ep->num_req, ep->nextpid, urbstat, cc, + ep->error_count); + } + goto out; + } + + switch (ep->nextpid) { + case USB_PID_OUT: + if (PTD_GET_COUNT(ptd) != ep->length) { + ERR("%s: count=%d len=%d\n", __FUNCTION__, + PTD_GET_COUNT(ptd), ep->length); + } + BUG_ON(PTD_GET_COUNT(ptd) != ep->length); + urb->actual_length += ep->length; + BUG_ON(urb->actual_length > urb->transfer_buffer_length); + usb_settoggle(udev, ep->epnum, 1, PTD_GET_TOGGLE(ptd)); + if (urb->actual_length == urb->transfer_buffer_length) { + DBG(3, "%s: req %d xfer complete %d/%d status %d -> 0\n", __func__, + ep->num_req, len, ep->maxpacket, urbstat); + if (usb_pipecontrol(urb->pipe)) { + DBG(3, "%s: req %d %s Wait for ACK\n", __FUNCTION__, + ep->num_req, + usb_pipein(urb->pipe) ? "IN" : "OUT"); + ep->nextpid = USB_PID_ACK; + } else { + if (len % ep->maxpacket || + !(urb->transfer_flags & URB_ZERO_PACKET)) { + urbstat = 0; + DBG(3, "%s: req %d URB %s status %d count %d/%d/%d\n", + __func__, ep->num_req, usb_pipein(urb->pipe) ? "IN" : "OUT", + urbstat, len, ep->maxpacket, urb->actual_length); + } + } + } + break; + case USB_PID_IN: + len = PTD_GET_COUNT(ptd); + BUG_ON(len > ep->length); + urb->actual_length += len; + BUG_ON(urb->actual_length > urb->transfer_buffer_length); + usb_settoggle(udev, ep->epnum, 0, PTD_GET_TOGGLE(ptd)); + // if transfer completed or (allowed) data underrun + if ((urb->transfer_buffer_length == urb->actual_length) || + len % ep->maxpacket) { + DBG(3, "%s: req %d xfer complete %d/%d status %d -> 0\n", __func__, + ep->num_req, len, ep->maxpacket, urbstat); + if (usb_pipecontrol(urb->pipe)) { + DBG(3, "%s: req %d %s Wait for ACK\n", __FUNCTION__, + ep->num_req, + usb_pipein(urb->pipe) ? "IN" : "OUT"); + ep->nextpid = USB_PID_ACK; + } else { + urbstat = 0; + DBG(3, "%s: req %d URB %s status %d count %d/%d/%d\n", + __func__, ep->num_req, usb_pipein(urb->pipe) ? "IN" : "OUT", + urbstat, len, ep->maxpacket, urb->actual_length); + } + } + break; + case USB_PID_SETUP: + if (urb->transfer_buffer_length == urb->actual_length) { + ep->nextpid = USB_PID_ACK; + } else if (usb_pipeout(urb->pipe)) { + usb_settoggle(udev, 0, 1, 1); + ep->nextpid = USB_PID_OUT; + } else { + usb_settoggle(udev, 0, 0, 1); + ep->nextpid = USB_PID_IN; + } + break; + case USB_PID_ACK: + DBG(3, "%s: req %d got ACK %d -> 0\n", __FUNCTION__, ep->num_req, + urbstat); + WARN_ON(urbstat != -EINPROGRESS); + urbstat = 0; + ep->nextpid = 0; + break; + default: + BUG_ON(1); + } + + out: + if (urbstat != -EINPROGRESS) { + DBG(2, "%s: Finishing ep %p req %d urb %p status %d\n", __FUNCTION__, + ep, ep->num_req, urb, urbstat); + finish_request(isp1362_hcd, ep, urb, regs, urbstat); + } +} + +static void finish_unlinks(struct isp1362_hcd *isp1362_hcd, struct pt_regs *regs) +{ + struct isp1362_ep *ep; + struct isp1362_ep *tmp; + + list_for_each_entry_safe(ep, tmp, &isp1362_hcd->remove_list, remove_list) { + struct isp1362_ep_queue *epq = + get_ptd_queue(isp1362_hcd, ep->ptd_offset); + int index = ep->ptd_index; + + BUG_ON(epq == NULL); + if (index >= 0) { + DBG(1, "%s: remove PTD[%d] $%04x\n", __FUNCTION__, index, ep->ptd_offset); + BUG_ON(ep->num_ptds == 0); + release_ptd_buffers(epq, ep); + } + if (!list_empty(&ep->hep->urb_list)) { + struct urb *urb = get_urb(ep); + + DBG(1, "%s: Finishing req %d ep %p from remove_list\n", __FUNCTION__, + ep->num_req, ep); + finish_request(isp1362_hcd, ep, urb, regs, -ESHUTDOWN); + } + WARN_ON(list_empty(&ep->active)); + if (!list_empty(&ep->active)) { + list_del_init(&ep->active); + DBG(1, "%s: ep %p removed from active list\n", __FUNCTION__, ep); + } + list_del_init(&ep->remove_list); + DBG(1, "%s: ep %p removed from remove_list\n", __FUNCTION__, ep); + } + DBG(1, "%s: Done\n", __FUNCTION__); +} + +static inline void enable_atl_transfers(struct isp1362_hcd *isp1362_hcd, int count) +{ + if (count > 0) { + if (count < isp1362_hcd->atl_queue.ptd_count) { + isp1362_write_reg16(isp1362_hcd, HCATLDTC, count); + } + isp1362_enable_int(isp1362_hcd, HCuPINT_ATL); + isp1362_write_reg32(isp1362_hcd, HCATLSKIP, isp1362_hcd->atl_queue.skip_map); + isp1362_set_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_ATL_ACTIVE); + } else { + isp1362_enable_int(isp1362_hcd, HCuPINT_SOF); + } +} + +static inline void enable_intl_transfers(struct isp1362_hcd *isp1362_hcd) +{ + isp1362_enable_int(isp1362_hcd, HCuPINT_INTL); + isp1362_set_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_INTL_ACTIVE); + isp1362_write_reg32(isp1362_hcd, HCINTLSKIP, isp1362_hcd->intl_queue.skip_map); +} + +static inline void enable_istl_transfers(struct isp1362_hcd *isp1362_hcd, int flip) +{ + isp1362_enable_int(isp1362_hcd, flip ? HCuPINT_ISTL1 : HCuPINT_ISTL0); + isp1362_set_mask16(isp1362_hcd, HCBUFSTAT, flip ? + HCBUFSTAT_ISTL1_FULL : HCBUFSTAT_ISTL0_FULL); +} + +static int submit_req(struct isp1362_hcd *isp1362_hcd, struct urb *urb, + struct isp1362_ep *ep, struct isp1362_ep_queue *epq) +{ + int index = epq->free_ptd; + + prepare_ptd(isp1362_hcd, urb, ep, epq, 0); + index = claim_ptd_buffers(epq, ep, ep->length); + if (index == -ENOMEM) { + DBG(1, "%s: req %d No free %s PTD available: %d, %08lx:%08lx\n", __FUNCTION__, + ep->num_req, epq->name, ep->num_ptds, epq->buf_map, epq->skip_map); + return index; + } else if (index == -EOVERFLOW) { + DBG(1, "%s: req %d Not enough space for %d byte %s PTD %d %08lx:%08lx\n", + __FUNCTION__, ep->num_req, ep->length, epq->name, ep->num_ptds, + epq->buf_map, epq->skip_map); + return index; + } else { + BUG_ON(index < 0); + } + list_add_tail(&ep->active, &epq->active); + DBG(1, "%s: ep %p req %d len %d added to active list %p\n", __FUNCTION__, + ep, ep->num_req, ep->length, &epq->active); + DBG(1, "%s: Submitting %s PTD $%04x for ep %p req %d\n", __FUNCTION__, epq->name, + ep->ptd_offset, ep, ep->num_req); + isp1362_write_ptd(isp1362_hcd, ep, epq); + __clear_bit(ep->ptd_index, &epq->skip_map); + + return 0; +} + +static void start_atl_transfers(struct isp1362_hcd *isp1362_hcd) +{ + int ptd_count = 0; + struct isp1362_ep_queue *epq = &isp1362_hcd->atl_queue; + struct isp1362_ep *ep; + int defer = 0; + + if (atomic_read(&epq->finishing)) { + DBG(1, "%s: finish_transfers is active for %s\n", __FUNCTION__, epq->name); + return; + } + + list_for_each_entry(ep, &isp1362_hcd->async, schedule) { + struct urb *urb = get_urb(ep); + int ret; + + if (!list_empty(&ep->active)) { + DBG(2, "%s: Skipping active %s ep %p\n", __FUNCTION__, epq->name, ep); + continue; + } + + DBG(1, "%s: Processing %s ep %p req %d\n", __FUNCTION__, epq->name, + ep, ep->num_req); + + ret = submit_req(isp1362_hcd, urb, ep, epq); + if (ret == -ENOMEM) { + defer = 1; + break; + } else if (ret == -EOVERFLOW) { + defer = 1; + continue; + } +#ifdef BUGGY_PXA2XX_UDC_USBTEST + defer = ep->nextpid == USB_PID_SETUP; +#endif + ptd_count++; + } + + /* Avoid starving of endpoints */ + if (isp1362_hcd->async.next != isp1362_hcd->async.prev) { + DBG(2, "%s: Cycling ASYNC schedule %d\n", __FUNCTION__, ptd_count); + list_move(&isp1362_hcd->async, isp1362_hcd->async.next); + } + if (ptd_count || defer) { + enable_atl_transfers(isp1362_hcd, defer ? 0 : ptd_count); + } + + epq->ptd_count += ptd_count; + if (epq->ptd_count > epq->stat_maxptds) { + epq->stat_maxptds = epq->ptd_count; + DBG(0, "%s: max_ptds: %d\n", __FUNCTION__, epq->stat_maxptds); + } +} + +static void start_intl_transfers(struct isp1362_hcd *isp1362_hcd) +{ + int ptd_count = 0; + struct isp1362_ep_queue *epq = &isp1362_hcd->intl_queue; + struct isp1362_ep *ep; + + if (atomic_read(&epq->finishing)) { + DBG(1, "%s: finish_transfers is active for %s\n", __FUNCTION__, epq->name); + return; + } + + list_for_each_entry(ep, &isp1362_hcd->periodic, schedule) { + struct urb *urb = get_urb(ep); + int ret; + + if (!list_empty(&ep->active)) { + DBG(1, "%s: Skipping active %s ep %p\n", __FUNCTION__, + epq->name, ep); + continue; + } + + DBG(1, "%s: Processing %s ep %p req %d\n", __FUNCTION__, + epq->name, ep, ep->num_req); + ret = submit_req(isp1362_hcd, urb, ep, epq); + if (ret == -ENOMEM) { + break; + } else if (ret == -EOVERFLOW) { + continue; + } + ptd_count++; + } + + if (ptd_count) { + static int last_count = 0; + + if (ptd_count != last_count) { + DBG(0, "%s: ptd_count: %d\n", __FUNCTION__, ptd_count); + last_count = ptd_count; + } + enable_intl_transfers(isp1362_hcd); + } + + epq->ptd_count += ptd_count; + if (epq->ptd_count > epq->stat_maxptds) { + epq->stat_maxptds = epq->ptd_count; + } +} + +static inline int next_ptd(struct isp1362_ep_queue *epq, struct isp1362_ep *ep) +{ + u16 ptd_offset = ep->ptd_offset; + int num_ptds = (ep->length + PTD_HEADER_SIZE + (epq->blk_size - 1)) / epq->blk_size; + + DBG(2, "%s: PTD offset $%04x + %04x => %d * %04x -> $%04x\n", __FUNCTION__, ptd_offset, + ep->length, num_ptds, epq->blk_size, ptd_offset + num_ptds * epq->blk_size); + + ptd_offset += num_ptds * epq->blk_size; + if (ptd_offset < epq->buf_start + epq->buf_size) { + return ptd_offset; + } else { + return -ENOMEM; + } +} + +static void start_iso_transfers(struct isp1362_hcd *isp1362_hcd) +{ + int ptd_count = 0; + int flip = isp1362_hcd->istl_flip; + struct isp1362_ep_queue *epq; + int ptd_offset; + struct isp1362_ep *ep; + struct isp1362_ep *tmp; + u16 fno = isp1362_read_reg32(isp1362_hcd, HCFMNUM); + + fill2: + epq = &isp1362_hcd->istl_queue[flip]; + if (atomic_read(&epq->finishing)) { + DBG(1, "%s: finish_transfers is active for %s\n", __FUNCTION__, epq->name); + return; + } + + if (!list_empty(&epq->active)) { + return; + } + + ptd_offset = epq->buf_start; + list_for_each_entry_safe(ep, tmp, &isp1362_hcd->isoc, schedule) { + struct urb *urb = get_urb(ep); + s16 diff = fno - (u16)urb->start_frame; + + DBG(1, "%s: Processing %s ep %p\n", __FUNCTION__, epq->name, ep); + + if (diff > urb->number_of_packets) { + // time frame for this URB has elapsed + finish_request(isp1362_hcd, ep, urb, NULL, -EOVERFLOW); + continue; + } else if (diff < -1) { + // URB is not due in this frame or the next one. + // Comparing with '-1' instead of '0' accounts for double + // buffering in the ISP1362 which enables us to queue the PTD + // one frame ahead of time + } else if (diff == -1) { + // submit PTD's that are due in the next frame + prepare_ptd(isp1362_hcd, urb, ep, epq, fno); + if (ptd_offset + PTD_HEADER_SIZE + ep->length > + epq->buf_start + epq->buf_size) { + ERR("%s: Not enough ISO buffer space for %d byte PTD\n", + __func__, ep->length); + continue; + } + ep->ptd_offset = ptd_offset; + list_add_tail(&ep->active, &epq->active); + + ptd_offset = next_ptd(epq, ep); + if (ptd_offset < 0) { + WARN("%s: req %d No more %s PTD buffers available\n", __func__, + ep->num_req, epq->name); + break; + } + } + } + list_for_each_entry(ep, &epq->active, active) { + if (epq->active.next == &ep->active) { + ep->ptd.mps |= PTD_LAST_MSK; + } + isp1362_write_ptd(isp1362_hcd, ep, epq); + ptd_count++; + } + + if (ptd_count) { + enable_istl_transfers(isp1362_hcd, flip); + } + + epq->ptd_count += ptd_count; + if (epq->ptd_count > epq->stat_maxptds) { + epq->stat_maxptds = epq->ptd_count; + } + + // check, whether the second ISTL buffer may also be filled + if (!(isp1362_read_reg16(isp1362_hcd, HCBUFSTAT) & + (flip ? HCBUFSTAT_ISTL0_FULL : HCBUFSTAT_ISTL1_FULL))) { + fno++; + ptd_count = 0; + flip = 1 - flip; + goto fill2; + } +} + +static void finish_transfers(struct isp1362_hcd *isp1362_hcd, unsigned long done_map, + struct isp1362_ep_queue *epq, struct pt_regs *regs) +{ + struct isp1362_ep *ep; + struct isp1362_ep *tmp; + + if (list_empty(&epq->active)) { + DBG(1, "%s: Nothing to do for %s queue\n", __FUNCTION__, epq->name); + return; + } + + DBG(1, "%s: Finishing %s transfers %08lx\n", __FUNCTION__, epq->name, done_map); + + atomic_inc(&epq->finishing); + list_for_each_entry_safe(ep, tmp, &epq->active, active) { + int index = ep->ptd_index; + + DBG(1, "%s: Checking %s PTD[%02x] $%04x\n", __FUNCTION__, epq->name, + index, ep->ptd_offset); + + BUG_ON(index < 0); + if (__test_and_clear_bit(index, &done_map)) { + isp1362_read_ptd(isp1362_hcd, ep, epq); + epq->free_ptd = index; + BUG_ON(ep->num_ptds == 0); + release_ptd_buffers(epq, ep); + + DBG(1, "%s: ep %p req %d removed from active list\n", __FUNCTION__, + ep, ep->num_req); + if (!list_empty(&ep->remove_list)) { + list_del_init(&ep->remove_list); + DBG(1, "%s: ep %p removed from remove list\n", __FUNCTION__, ep); + } + DBG(1, "%s: Postprocessing %s ep %p req %d\n", __FUNCTION__, epq->name, + ep, ep->num_req); + postproc_ep(isp1362_hcd, ep, regs); + } + if (!done_map) { + break; + } + } + if (done_map) { + WARN("%s: done_map not clear: %08lx:%08lx\n", __FUNCTION__, done_map, + epq->skip_map); + } + atomic_dec(&epq->finishing); +} + +static void finish_iso_transfers(struct isp1362_hcd *isp1362_hcd, struct isp1362_ep_queue *epq, + struct pt_regs *regs) +{ + struct isp1362_ep *ep; + struct isp1362_ep *tmp; + + if (list_empty(&epq->active)) { + DBG(1, "%s: Nothing to do for %s queue\n", __FUNCTION__, epq->name); + return; + } + + DBG(1, "%s: Finishing %s transfers\n", __FUNCTION__, epq->name); + + atomic_inc(&epq->finishing); + list_for_each_entry_safe(ep, tmp, &epq->active, active) { + DBG(1, "%s: Checking PTD $%04x\n", __FUNCTION__, ep->ptd_offset); + + isp1362_read_ptd(isp1362_hcd, ep, epq); + DBG(1, "%s: Postprocessing %s ep %p\n", __FUNCTION__, epq->name, ep); + postproc_ep(isp1362_hcd, ep, regs); + } + WARN_ON(epq->blk_size != 0); + atomic_dec(&epq->finishing); +} + +static irqreturn_t isp1362_irq(struct usb_hcd *hcd, struct pt_regs *regs) +{ + int handled = 0; + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + u16 irqstat; + u16 svc_mask; + + spin_lock(&isp1362_hcd->lock); + + BUG_ON(isp1362_hcd->irq_active++); + + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, 0); + + irqstat = isp1362_read_reg16(isp1362_hcd, HCuPINT); + DBG(3, "%s: got IRQ %04x:%04x\n", __FUNCTION__, irqstat, isp1362_hcd->irqenb); + + // only handle interrupts that are currently enabled + irqstat &= isp1362_hcd->irqenb; + isp1362_write_reg16(isp1362_hcd, HCuPINT, irqstat); + svc_mask = irqstat; + + if (irqstat & HCuPINT_SOF) { + isp1362_hcd->irqenb &= ~HCuPINT_SOF; + isp1362_hcd->irq_stat[ISP1362_INT_SOF]++; + handled = 1; + svc_mask &= ~HCuPINT_SOF; + DBG(3, "%s: SOF\n", __FUNCTION__); + isp1362_hcd->fmindex = isp1362_read_reg32(isp1362_hcd, HCFMNUM); + if (!list_empty(&isp1362_hcd->remove_list)) { + finish_unlinks(isp1362_hcd, regs); + } + if (!list_empty(&isp1362_hcd->async) && !(irqstat & HCuPINT_ATL)) { + if (list_empty(&isp1362_hcd->atl_queue.active)) { + start_atl_transfers(isp1362_hcd); + } else { + isp1362_enable_int(isp1362_hcd, HCuPINT_ATL); + isp1362_write_reg32(isp1362_hcd, HCATLSKIP, + isp1362_hcd->atl_queue.skip_map); + isp1362_set_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_ATL_ACTIVE); + } + } + } + + if (irqstat & HCuPINT_ISTL0) { + isp1362_hcd->irq_stat[ISP1362_INT_ISTL0]++; + handled = 1; + svc_mask &= ~HCuPINT_ISTL0; + isp1362_clr_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_ISTL0_FULL); + DBG(1, "%s: ISTL0\n", __FUNCTION__); + WARN_ON(isp1362_hcd->istl_flip); + WARN_ON(isp1362_read_reg16(isp1362_hcd, HCBUFSTAT) & HCBUFSTAT_ISTL0_ACTIVE); + WARN_ON(!isp1362_read_reg16(isp1362_hcd, HCBUFSTAT) & HCBUFSTAT_ISTL0_DONE); + isp1362_hcd->irqenb &= ~HCuPINT_ISTL0; + } + + if (irqstat & HCuPINT_ISTL1) { + isp1362_hcd->irq_stat[ISP1362_INT_ISTL1]++; + handled = 1; + svc_mask &= ~HCuPINT_ISTL1; + isp1362_clr_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_ISTL1_FULL); + DBG(1, "%s: ISTL1\n", __FUNCTION__); + WARN_ON(!isp1362_hcd->istl_flip); + WARN_ON(isp1362_read_reg16(isp1362_hcd, HCBUFSTAT) & HCBUFSTAT_ISTL1_ACTIVE); + WARN_ON(!isp1362_read_reg16(isp1362_hcd, HCBUFSTAT) & HCBUFSTAT_ISTL1_DONE); + isp1362_hcd->irqenb &= ~HCuPINT_ISTL1; + } + + if (irqstat & (HCuPINT_ISTL0 | HCuPINT_ISTL1)) { + WARN_ON((irqstat & (HCuPINT_ISTL0 | HCuPINT_ISTL1)) == + (HCuPINT_ISTL0 | HCuPINT_ISTL1)); + finish_iso_transfers(isp1362_hcd, + &isp1362_hcd->istl_queue[isp1362_hcd->istl_flip], regs); + start_iso_transfers(isp1362_hcd); + isp1362_hcd->istl_flip = 1 - isp1362_hcd->istl_flip; + } + + if (irqstat & HCuPINT_INTL) { + u32 done_map = isp1362_read_reg32(isp1362_hcd, HCINTLDONE); + u32 skip_map = isp1362_read_reg32(isp1362_hcd, HCINTLSKIP); + isp1362_hcd->irq_stat[ISP1362_INT_INTL]++; + + DBG(2, "%s: INTL\n", __FUNCTION__); + + svc_mask &= ~HCuPINT_INTL; + + isp1362_write_reg32(isp1362_hcd, HCINTLSKIP, skip_map | done_map); + if (~(done_map | skip_map) == 0) { + // All PTDs are finished, disable INTL processing entirely + isp1362_clr_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_INTL_ACTIVE); + } + + handled = 1; + WARN_ON(!done_map); + if (done_map) { + DBG(3, "%s: INTL done_map %08x\n", __func__, done_map); + finish_transfers(isp1362_hcd, done_map, &isp1362_hcd->intl_queue, regs); + start_intl_transfers(isp1362_hcd); + } + } + + if (irqstat & HCuPINT_ATL) { + u32 done_map = isp1362_read_reg32(isp1362_hcd, HCATLDONE); + u32 skip_map = isp1362_read_reg32(isp1362_hcd, HCATLSKIP); + isp1362_hcd->irq_stat[ISP1362_INT_ATL]++; + + DBG(2, "%s: ATL\n", __FUNCTION__); + + svc_mask &= ~HCuPINT_ATL; + + isp1362_write_reg32(isp1362_hcd, HCATLSKIP, skip_map | done_map); + if (~(done_map | skip_map) == 0) { + isp1362_clr_mask16(isp1362_hcd, HCBUFSTAT, HCBUFSTAT_ATL_ACTIVE); + } + if (done_map) { + DBG(3, "%s: ATL done_map %08x\n", __func__, done_map); + finish_transfers(isp1362_hcd, done_map, &isp1362_hcd->atl_queue, regs); + start_atl_transfers(isp1362_hcd); + } + } + + if (irqstat & HCuPINT_OPR) { + u32 intstat = isp1362_read_reg32(isp1362_hcd, HCINTSTAT); + isp1362_hcd->irq_stat[ISP1362_INT_OPR]++; + + svc_mask &= ~HCuPINT_OPR; + DBG(2, "%s: OPR %08x:%08x\n", __FUNCTION__, intstat, isp1362_hcd->intenb); + intstat &= isp1362_hcd->intenb; + if (intstat & OHCI_INTR_UE) { + ERR("Unrecoverable error\n"); + // FIXME: do here reset or cleanup or whatever + } + if (intstat & OHCI_INTR_RHSC) { + isp1362_hcd->rhstatus = isp1362_read_reg32(isp1362_hcd, HCRHSTATUS); + isp1362_hcd->rhport[0] = isp1362_read_reg32(isp1362_hcd, HCRHPORT1); +#if MAX_ROOT_PORTS > 1 + isp1362_hcd->rhport[1] = isp1362_read_reg32(isp1362_hcd, HCRHPORT2); +#else + isp1362_hcd->rhport[1] = 0; +#endif + } + if (intstat & OHCI_INTR_RD) { + INFO("%s: RESUME DETECTED\n", __FUNCTION__); + isp1362_show_reg(isp1362_hcd, HCCONTROL); + if (hcd->state != HC_STATE_QUIESCING) + schedule_work(&isp1362_hcd->rh_resume); + } + isp1362_write_reg32(isp1362_hcd, HCINTSTAT, intstat); + irqstat &= ~HCuPINT_OPR; + handled = 1; + } + + if (irqstat & HCuPINT_SUSP) { + isp1362_hcd->irq_stat[ISP1362_INT_SUSP]++; + handled = 1; + svc_mask &= ~HCuPINT_SUSP; + + INFO("%s: SUSPEND IRQ\n", __FUNCTION__); + } + + if (irqstat & HCuPINT_CLKRDY) { + isp1362_hcd->irq_stat[ISP1362_INT_CLKRDY]++; + handled = 1; + isp1362_hcd->irqenb &= ~HCuPINT_CLKRDY; + svc_mask &= ~HCuPINT_CLKRDY; + INFO("%s: CLKRDY IRQ\n", __FUNCTION__); + } + + if (svc_mask) { + ERR("%s: Unserviced interrupt(s) %04x\n", __func__, svc_mask); + } + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, isp1362_hcd->irqenb); + isp1362_hcd->irq_active--; + spin_unlock(&isp1362_hcd->lock); + + return IRQ_RETVAL(handled); +} + +/*-------------------------------------------------------------------------*/ + +#define MAX_PERIODIC_LOAD 900 // out of 1000 usec +static int balance(struct isp1362_hcd *isp1362_hcd, u16 interval, u16 load) +{ + int i, branch = -ENOSPC; + + // search for the least loaded schedule branch of that interval + // which has enough bandwidth left unreserved. + for (i = 0; i < interval; i++) { + if (branch < 0 || isp1362_hcd->load[branch] > isp1362_hcd->load[i]) { + int j; + + for (j = i; j < PERIODIC_SIZE; j += interval) { + if ((isp1362_hcd->load[j] + load) > MAX_PERIODIC_LOAD) { + ERR("%s: new load %d load[%02x] %d max %d\n", __FUNCTION__, + load, j, isp1362_hcd->load[j], MAX_PERIODIC_LOAD); + break; + } + } + if (j < PERIODIC_SIZE) { + continue; + } + branch = i; + } + } + return branch; +} + +/* NB! ALL the code above this point runs with isp1362_hcd->lock + held, irqs off +*/ + +/*-------------------------------------------------------------------------*/ + +static int isp1362_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *hep, + struct urb *urb, unsigned int mem_flags) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + struct usb_device *udev = urb->dev; + unsigned int pipe = urb->pipe; + int is_out = !usb_pipein(pipe); + int type = usb_pipetype(pipe); + int epnum = usb_pipeendpoint(pipe); + struct isp1362_ep *ep = NULL; + unsigned long flags; + int retval = 0; + + DBG(3, "%s: urb %p\n", __func__, urb); + + if (type == PIPE_ISOCHRONOUS) { + ERR("Isochronous transfers not supported\n"); + return -ENOSPC; + } + + URB_DBG("%s: FA %d ep%d%s %s: len %d %s%s\n", __func__, + usb_pipedevice(pipe), epnum, + is_out ? "out" : "in", + ({ + char *s; + if (usb_pipecontrol(pipe)) { + s = "ctrl"; + } else if(usb_pipeint(pipe)) { + s = "int"; + } else if(usb_pipebulk(pipe)) { + s = "bulk"; + } else { + s = "iso"; + } + s;}), + urb->transfer_buffer_length, + (urb->transfer_flags & URB_ZERO_PACKET) ? "ZERO_PACKET " : "", + !(urb->transfer_flags & URB_SHORT_NOT_OK) ? + "short_ok" : ""); + + // avoid all allocations within spinlocks: request or endpoint + if (!hep->hcpriv) { + ep = kcalloc(1, sizeof *ep, mem_flags); + } + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + /* don't submit to a dead or disabled port */ +#if MAX_ROOT_PORTS > 1 + if (!((isp1362_hcd->rhport[0] | isp1362_hcd->rhport[1]) & +#else + if (!((isp1362_hcd->rhport[0]) & +#endif + (1 << USB_PORT_FEAT_ENABLE)) || + !HC_IS_RUNNING(hcd->state)) { + retval = -ENODEV; + goto fail; + } + + if (hep->hcpriv) { + kfree(ep); + ep = hep->hcpriv; + } else if (!ep) { + retval = -ENOMEM; + goto fail; + } else { + INIT_LIST_HEAD(&ep->schedule); + INIT_LIST_HEAD(&ep->active); + INIT_LIST_HEAD(&ep->remove_list); + ep->udev = usb_get_dev(udev); + ep->hep = hep; + ep->epnum = epnum; + ep->maxpacket = usb_maxpacket(udev, urb->pipe, is_out); + ep->ptd_offset = -EINVAL; + ep->ptd_index = -EINVAL; + usb_settoggle(udev, epnum, is_out, 0); + + if (type == PIPE_CONTROL) { + ep->nextpid = USB_PID_SETUP; + } else if (is_out) { + ep->nextpid = USB_PID_OUT; + } else { + ep->nextpid = USB_PID_IN; + } + + switch (type) { + case PIPE_ISOCHRONOUS: + case PIPE_INTERRUPT: + if (urb->interval > PERIODIC_SIZE) { + urb->interval = PERIODIC_SIZE; + } + ep->interval = urb->interval; + ep->branch = PERIODIC_SIZE; + ep->load = usb_calc_bus_time(udev->speed, !is_out, + (type == PIPE_ISOCHRONOUS), + usb_maxpacket(udev, pipe, is_out)) / 1000; + break; + } + hep->hcpriv = ep; + } + ep->num_req = isp1362_hcd->req_serial++; + + /* maybe put endpoint into schedule */ + switch (type) { + case PIPE_CONTROL: + case PIPE_BULK: + if (list_empty(&ep->schedule)) { + DBG(1, "%s: Adding ep %p req %d to async schedule\n", + __FUNCTION__, ep, ep->num_req); + list_add_tail(&ep->schedule, &isp1362_hcd->async); + } + break; + case PIPE_ISOCHRONOUS: + case PIPE_INTERRUPT: + urb->interval = ep->interval; + + // urb submitted for already existing EP + if (ep->branch < PERIODIC_SIZE) { + break; + } + + retval = balance(isp1362_hcd, ep->interval, ep->load); + if (retval < 0) { + ERR("%s: balance returned %d\n", __FUNCTION__, retval); + goto fail; + } + ep->branch = retval; + retval = 0; + isp1362_hcd->fmindex = isp1362_read_reg32(isp1362_hcd, HCFMNUM); + DBG(1, "%s: Current frame %04x branch %02x start_frame %04x(%04x)\n", + __FUNCTION__, isp1362_hcd->fmindex, ep->branch, + ((isp1362_hcd->fmindex + PERIODIC_SIZE - 1) & + ~(PERIODIC_SIZE - 1)) + ep->branch, + (isp1362_hcd->fmindex & (PERIODIC_SIZE - 1)) + ep->branch); + + if (list_empty(&ep->schedule)) { + if (type == PIPE_ISOCHRONOUS) { + u16 frame = isp1362_hcd->fmindex; + + frame += max_t(u16, 8, ep->interval); + frame &= ~(ep->interval - 1); + frame |= ep->branch; + if (frame_before(frame, isp1362_hcd->fmindex)) { + frame += ep->interval; + } + urb->start_frame = frame; + + DBG(1, "%s: Adding ep %p to isoc schedule\n", __func__, ep); + list_add_tail(&ep->schedule, &isp1362_hcd->isoc); + } else { + DBG(1, "%s: Adding ep %p to periodic schedule\n", __func__, ep); + list_add_tail(&ep->schedule, &isp1362_hcd->periodic); + } + } else { + DBG(1, "%s: ep %p already scheduled\n", __func__, ep); + } + usb_claim_bandwidth(udev, urb, ep->load / ep->interval, type == PIPE_ISOCHRONOUS); + DBG(2, "%s: load %d bandwidth %d -> %d\n", __FUNCTION__, + ep->load / ep->interval, isp1362_hcd->load[ep->branch], + isp1362_hcd->load[ep->branch] + ep->load); + isp1362_hcd->load[ep->branch] += ep->load; + } + + /* in case of unlink-during-submit */ + spin_lock(&urb->lock); + if (urb->status != -EINPROGRESS) { + spin_unlock(&urb->lock); + WARN("%s: Finishing ep %p req %d before submission with status %08x\n", + __func__, ep, ep->num_req, urb->status); + finish_request(isp1362_hcd, ep, urb, NULL, 0); + retval = 0; + goto fail; + } + urb->hcpriv = hep; + ALIGNSTAT(isp1362_hcd, urb->transfer_buffer); + spin_unlock(&urb->lock); + + switch (type) { + case PIPE_CONTROL: + case PIPE_BULK: + start_atl_transfers(isp1362_hcd); + break; + case PIPE_INTERRUPT: + start_intl_transfers(isp1362_hcd); + break; + case PIPE_ISOCHRONOUS: + start_iso_transfers(isp1362_hcd); + break; + default: + BUG(); + } + + fail: + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + if (retval) { + DBG(0, "%s: urb %p failed with %d\n", __FUNCTION__, urb, retval); + } + return retval; +} + +static int isp1362_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + struct usb_host_endpoint *hep; + unsigned long flags; + struct isp1362_ep *ep; + int retval = 0; + + DBG(3, "%s: urb %p\n", __func__, urb); + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + hep = urb->hcpriv; + if (!hep) { + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + return -EIDRM; + } + + ep = hep->hcpriv; + if (ep) { + // In front of queue? + if (ep->hep->urb_list.next == &urb->urb_list) { + if (!list_empty(&ep->active)) { + DBG(1, "%s: urb %p ep %p req %d active PTD[%d] $%04x\n", __func__, + urb, ep, ep->num_req, ep->ptd_index, ep->ptd_offset); + // disable processing and queue PTD for removal + remove_ptd(isp1362_hcd, ep); + urb = NULL; + } + } + if (urb) { + DBG(1, "%s: Finishing ep %p req %d\n", __func__, ep, + ep->num_req); + finish_request(isp1362_hcd, ep, urb, NULL, -ESHUTDOWN); + } else { + DBG(1, "%s: urb %p active; wait4irq\n", __func__, urb); + } + } else { + WARN("%s: No EP in URB %p\n", __FUNCTION__, urb); + retval = -EINVAL; + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + DBG(3, "%s: exit\n",__func__); + + return retval; +} + +static void isp1362_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) +{ + struct isp1362_ep *ep = hep->hcpriv; + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long flags; + + DBG(1, "%s: ep %p\n", __func__, ep); + if (!ep) { + return; + } + spin_lock_irqsave(&isp1362_hcd->lock, flags); + if (!list_empty(&hep->urb_list)) { + if (!list_empty(&ep->active) && list_empty(&ep->remove_list)) { + DBG(1, "%s: Removing ep %p req %d PTD[%d] $%04x\n", __FUNCTION__, + ep, ep->num_req, ep->ptd_index, ep->ptd_offset); + remove_ptd(isp1362_hcd, ep); + INFO("%s: Waiting for Interrupt to clean up\n", __FUNCTION__); + } + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + // Wait for interrupt to clear out active list + while (!list_empty(&ep->active)) { + msleep(1); + } + + DBG(1, "%s: Freeing EP %p\n", __FUNCTION__, ep); + + usb_put_dev(ep->udev); + kfree(ep); + hep->hcpriv = NULL; +} + +static int isp1362_get_frame(struct usb_hcd *hcd) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + u32 fmnum; + unsigned long flags; + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + fmnum = isp1362_read_reg32(isp1362_hcd, HCFMNUM); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + return (int)fmnum; +} + +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_PM) +static int isp1362_hub_suspend(struct usb_hcd *hcd); +// Adapted from ohci-hub.c +#endif + +static int isp1362_hub_status_data(struct usb_hcd *hcd, char *buf) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + int ports, i, changed = 0; + int can_suspend = hcd->can_wakeup; + + if (!HC_IS_RUNNING(hcd->state)) { + return -ESHUTDOWN; + } + +#if MAX_ROOT_PORTS > 1 + ports = isp1362_hcd->rhdesca & RH_A_NDP; +#else + if((isp1362_hcd->rhdesca & RH_A_NDP) == 0) + ports = 0; + else + ports = 1; +#endif + BUG_ON(ports > 2); + + /* init status */ + if (isp1362_hcd->rhstatus & (RH_HS_LPSC | RH_HS_OCIC)) { + buf[0] = changed = 1; + } else { + buf[0] = 0; + } + + for (i = 0; i < ports; i++) { + u32 status = isp1362_hcd->rhport[i]; + + if (status & (RH_PS_CSC | RH_PS_PESC | RH_PS_PSSC | + RH_PS_OCIC | RH_PS_PRSC)) { + changed = 1; + buf[0] |= 1 << (i + 1); + continue; + } + + if (!(status & RH_PS_CCS)) { + continue; + } + if ((status & RH_PS_PSS) && hcd->remote_wakeup) { + continue; + } + can_suspend = 0; + } +#if defined(CONFIG_USB_SUSPEND) || defined(CONFIG_PM) + if (can_suspend && !changed && + list_empty(&isp1362_hcd->async) && + list_empty(&isp1362_hcd->periodic) && + list_empty(&isp1362_hcd->isoc) && + (isp1362_read_reg32(isp1362_hcd, HCCONTROL) & OHCI_CTRL_HCFS) == OHCI_USB_OPER && + time_after(jiffies, isp1362_hcd->next_statechange) && + usb_trylock_device(hcd->self.root_hub)) { + DBG(0, "%s: Autosuspending root hub\n", __FUNCTION__); + isp1362_set_mask16(isp1362_hcd, HCHWCFG, HCHWCFG_CLKNOTSTOP); + (void) isp1362_hub_suspend(hcd); + hcd->state = HC_STATE_RUNNING; + usb_unlock_device(hcd->self.root_hub); + } +#endif + return changed; +} + +static void isp1362_hub_descriptor(struct isp1362_hcd *isp1362_hcd, + struct usb_hub_descriptor *desc) +{ + u32 reg = isp1362_hcd->rhdesca; + + DBG(3, "%s: enter\n", __func__); + + desc->bDescriptorType = 0x29; + desc->bDescLength = 9; + desc->bHubContrCurrent = 0; +#if MAX_ROOT_PORTS > 1 + desc->bNbrPorts = reg & 0x3; +#else + if((reg & 0x3) == 0) + desc->bNbrPorts = 0; + else + desc->bNbrPorts = 1; +#endif + // Power switching, device type, overcurrent. + desc->wHubCharacteristics = cpu_to_le16((reg >> 8) & 0x1f); + DBG(0, "%s: hubcharacteristics = %02x\n", __FUNCTION__, cpu_to_le16((reg >> 8) & 0x1f)); + desc->bPwrOn2PwrGood = (reg >> 24) & 0xff; + // two bitmaps: ports removable, and legacy PortPwrCtrlMask + desc->bitmap[0] = desc->bNbrPorts == 0 ? 0 : 1 ? 1 << 1 : 3 << 1; + desc->bitmap[1] = ~0; + + DBG(3, "%s: exit\n", __func__); +} + +// Adapted from ohci-hub.c +static int isp1362_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + u16 wIndex, char *buf, u16 wLength) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + int retval = 0; + unsigned long flags; + unsigned long t1; + int ports; + u32 tmp = 0; + +#if MAX_ROOT_PORTS > 1 + ports = isp1362_hcd->rhdesca & RH_A_NDP; +#else + if((isp1362_hcd->rhdesca & RH_A_NDP) == 0) + ports = 0; + else + ports = 1; +#endif + BUG_ON(ports > 2); + + switch (typeReq) { + case ClearHubFeature: + DBG(0, "ClearHubFeature: "); + switch (wValue) { + case C_HUB_OVER_CURRENT: + _DBG(0, "C_HUB_OVER_CURRENT\n"); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_reg32(isp1362_hcd, HCRHSTATUS, RH_HS_OCIC); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + case C_HUB_LOCAL_POWER: + _DBG(0, "C_HUB_LOCAL_POWER\n"); + break; + default: + goto error; + } + break; + case SetHubFeature: + DBG(0, "SetHubFeature: "); + switch (wValue) { + case C_HUB_OVER_CURRENT: + case C_HUB_LOCAL_POWER: + _DBG(0, "C_HUB_OVER_CURRENT or C_HUB_LOCAL_POWER\n"); + break; + default: + goto error; + } + break; + case GetHubDescriptor: + DBG(0, "GetHubDescriptor\n"); + isp1362_hub_descriptor(isp1362_hcd, (struct usb_hub_descriptor *)buf); + break; + case GetHubStatus: + DBG(0, "GetHubStatus\n"); + *(__le32 *) buf = cpu_to_le32(0); + break; + case GetPortStatus: +#ifndef VERBOSE + DBG(0, "GetPortStatus\n"); +#endif + if (!wIndex || wIndex > ports) { + goto error; + } + tmp = isp1362_hcd->rhport[--wIndex]; + *(__le32 *) buf = cpu_to_le32(tmp); +#ifndef VERBOSE + if (*(u16 *) (buf + 2)) /* only if wPortChange is interesting */ +#endif + DBG(0, "GetPortStatus: port[%d] %08x\n", wIndex + 1, tmp); + break; + case ClearPortFeature: + DBG(0, "ClearPortFeature: "); + if (!wIndex || wIndex > ports) { + goto error; + } + wIndex--; + + switch (wValue) { + case USB_PORT_FEAT_ENABLE: + _DBG(0, "USB_PORT_FEAT_ENABLE\n"); + tmp = RH_PS_CCS; + break; + case USB_PORT_FEAT_C_ENABLE: + _DBG(0, "USB_PORT_FEAT_C_ENABLE\n"); + tmp = RH_PS_PESC; + break; + case USB_PORT_FEAT_SUSPEND: + _DBG(0, "USB_PORT_FEAT_SUSPEND\n"); + tmp = RH_PS_POCI; + if ((isp1362_hcd->hc_control & OHCI_CTRL_HCFS) != OHCI_USB_OPER) { + schedule_work(&isp1362_hcd->rh_resume); + } + break; + case USB_PORT_FEAT_C_SUSPEND: + _DBG(0, "USB_PORT_FEAT_C_SUSPEND\n"); + tmp = RH_PS_PSSC; + break; + case USB_PORT_FEAT_POWER: + _DBG(0, "USB_PORT_FEAT_POWER\n"); + tmp = RH_PS_LSDA; + + break; + case USB_PORT_FEAT_C_CONNECTION: + _DBG(0, "USB_PORT_FEAT_C_CONNECTION\n"); + tmp = RH_PS_CSC; + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + _DBG(0, "USB_PORT_FEAT_C_OVER_CURRENT\n"); + tmp = RH_PS_OCIC; + break; + case USB_PORT_FEAT_C_RESET: + _DBG(0, "USB_PORT_FEAT_C_RESET\n"); + tmp = RH_PS_PRSC; + break; + default: + goto error; + } + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + wIndex, tmp); + isp1362_hcd->rhport[wIndex] = + isp1362_read_reg32(isp1362_hcd, HCRHPORT1 + wIndex); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + break; + case SetPortFeature: + DBG(0, "SetPortFeature: "); + if (!wIndex || wIndex > ports) { + goto error; + } + wIndex--; + switch (wValue) { + case USB_PORT_FEAT_SUSPEND: + _DBG(0, "USB_PORT_FEAT_SUSPEND\n"); +#ifdef CONFIG_USB_OTG + if (ohci->hcd.self.otg_port == (wIndex + 1) && + ohci->hcd.self.b_hnp_enable) { + start_hnp(ohci); + break; + } +#endif + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + wIndex, RH_PS_PSS); + isp1362_hcd->rhport[wIndex] = + isp1362_read_reg32(isp1362_hcd, HCRHPORT1 + wIndex); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + break; + case USB_PORT_FEAT_POWER: + _DBG(0, "USB_PORT_FEAT_POWER\n"); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + wIndex, RH_PS_PPS); + isp1362_hcd->rhport[wIndex] = + isp1362_read_reg32(isp1362_hcd, HCRHPORT1 + wIndex); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + break; + case USB_PORT_FEAT_RESET: + _DBG(0, "USB_PORT_FEAT_RESET\n"); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + t1 = jiffies + msecs_to_jiffies(USB_RESET_WIDTH); + while (time_before(jiffies, t1)) { + // spin until any current reset finishes + for (;;) { + tmp = isp1362_read_reg32(isp1362_hcd, HCRHPORT1 + wIndex); + if (!(tmp & RH_PS_PRS)) { + break; + } + udelay(500); + } + if (!(tmp & RH_PS_CCS)) { + break; + } + // Reset lasts 10ms (claims datasheet) + isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + wIndex, (RH_PS_PRS)); + + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + msleep(10); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + } + + isp1362_hcd->rhport[wIndex] = isp1362_read_reg32(isp1362_hcd, + HCRHPORT1 + wIndex); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + break; + default: + goto error; + } + break; + + default: + error: + /* "protocol stall" on error */ + _DBG(0, "PROTOCOL STALL\n"); + retval = -EPIPE; + } + + return retval; +} + +#ifdef CONFIG_PM +static int isp1362_hub_suspend(struct usb_hcd *hcd) +{ + int status = 0; + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long flags; + + if (time_before(jiffies, isp1362_hcd->next_statechange)) { + msleep(5); + } + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + isp1362_hcd->hc_control = isp1362_read_reg32(isp1362_hcd, HCCONTROL); + switch (isp1362_hcd->hc_control & OHCI_CTRL_HCFS) { + case OHCI_USB_RESUME: + DBG(0, "%s: resume/suspend?\n", __FUNCTION__); + isp1362_hcd->hc_control &= ~OHCI_CTRL_HCFS; + isp1362_hcd->hc_control |= OHCI_USB_RESET; + isp1362_write_reg32(isp1362_hcd, HCCONTROL, isp1362_hcd->hc_control); + /* FALL THROUGH */ + case OHCI_USB_RESET: + status = -EBUSY; + WARN("%s: needs reinit!\n", __FUNCTION__); + goto done; + case OHCI_USB_SUSPEND: + WARN("%s: already suspended?\n", __FUNCTION__); + goto done; + } + DBG(0, "%s: suspend root hub\n", __FUNCTION__); + + /* First stop any processing */ + hcd->state = HC_STATE_QUIESCING; + if (!list_empty(&isp1362_hcd->atl_queue.active) || + !list_empty(&isp1362_hcd->intl_queue.active) || + !list_empty(&isp1362_hcd->istl_queue[0].active) || + !list_empty(&isp1362_hcd->istl_queue[1].active)) { + int limit; + + isp1362_write_reg32(isp1362_hcd, HCATLSKIP, ~0); + isp1362_write_reg32(isp1362_hcd, HCINTLSKIP, ~0); + isp1362_write_reg16(isp1362_hcd, HCBUFSTAT, 0); + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, 0); + isp1362_write_reg32(isp1362_hcd, HCINTSTAT, OHCI_INTR_SF); + + DBG(0, "%s: stopping schedules ...\n", __FUNCTION__); + limit = 2000; + while (limit > 0) { + udelay(250); + limit =- 250; + if (isp1362_read_reg32(isp1362_hcd, HCINTSTAT) & OHCI_INTR_SF) { + break; + } + } + mdelay(7); + if (isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_ATL) { + u32 done_map = isp1362_read_reg32(isp1362_hcd, HCATLDONE); + finish_transfers(isp1362_hcd, done_map, &isp1362_hcd->atl_queue, NULL); + } + if (isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_INTL) { + u32 done_map = isp1362_read_reg32(isp1362_hcd, HCINTLDONE); + finish_transfers(isp1362_hcd, done_map, &isp1362_hcd->intl_queue, NULL); + } + if (isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_ISTL0) { + finish_iso_transfers(isp1362_hcd, &isp1362_hcd->istl_queue[0], NULL); + } + if (isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_ISTL1) { + finish_iso_transfers(isp1362_hcd, &isp1362_hcd->istl_queue[1], NULL); + } + } + DBG(0, "%s: HCINTSTAT: %08x\n", __FUNCTION__, + isp1362_read_reg32(isp1362_hcd, HCINTSTAT)); + isp1362_write_reg32(isp1362_hcd, HCINTSTAT, + isp1362_read_reg32(isp1362_hcd, HCINTSTAT)); + + /* Suspend hub */ + isp1362_hcd->hc_control = OHCI_USB_SUSPEND; + /* maybe resume can wake root hub */ + if (hcd->remote_wakeup) { + DBG(0, "%s: Enabling RWE\n", __FUNCTION__); + isp1362_hcd->hc_control |= OHCI_CTRL_RWE; + } + isp1362_show_reg(isp1362_hcd, HCCONTROL); + isp1362_write_reg32(isp1362_hcd, HCCONTROL, isp1362_hcd->hc_control); + isp1362_show_reg(isp1362_hcd, HCCONTROL); + +#if 1 + isp1362_hcd->hc_control = isp1362_read_reg32(isp1362_hcd, HCCONTROL); + if ((isp1362_hcd->hc_control & OHCI_CTRL_HCFS) != OHCI_USB_SUSPEND) { + ERR("%s: controller won't suspend %08x\n", __FUNCTION__, + isp1362_hcd->hc_control); + status = -EBUSY; + } else { +#else + if (1) { +#endif + /* no resumes until devices finish suspending */ + isp1362_hcd->next_statechange = jiffies + msecs_to_jiffies(5); + } +done: + if (status == 0) { + hcd->state = HC_STATE_SUSPENDED; + DBG(0, "%s: HCD suspended: %08x\n", __FUNCTION__, + isp1362_read_reg32(isp1362_hcd, HCCONTROL)); + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + return status; +} + +static int isp1362_hub_resume(struct usb_hcd *hcd) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + u32 port; + unsigned long flags; + int status = -EINPROGRESS; + + if (time_before(jiffies, isp1362_hcd->next_statechange)) { + msleep(5); + } + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_hcd->hc_control = isp1362_read_reg32(isp1362_hcd, HCCONTROL); + INFO("%s: HCCONTROL: %08x\n", __FUNCTION__, isp1362_hcd->hc_control); + if (hcd->state == HC_STATE_RESUMING) { + WARN("%s: duplicate resume\n", __FUNCTION__); + status = 0; + } else switch (isp1362_hcd->hc_control & OHCI_CTRL_HCFS) { + case OHCI_USB_SUSPEND: + DBG(0, "%s: resume root hub\n", __FUNCTION__); + isp1362_hcd->hc_control &= ~OHCI_CTRL_HCFS; + isp1362_hcd->hc_control |= OHCI_USB_RESUME; + isp1362_write_reg32(isp1362_hcd, HCCONTROL, isp1362_hcd->hc_control); + break; + case OHCI_USB_RESUME: + /* HCFS changes sometime after INTR_RD */ + DBG(0, "%s: remote wakeup\n", __FUNCTION__); + break; + case OHCI_USB_OPER: + DBG(0, "%s: odd resume\n", __FUNCTION__); + status = 0; + hcd->self.root_hub->dev.power.power_state = PMSG_ON; + break; + default: /* RESET, we lost power */ + DBG(0, "%s: root hub hardware reset\n", __FUNCTION__); + status = -EBUSY; + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + if (status == -EBUSY) { + DBG(0, "%s: Restarting HC\n", __FUNCTION__); + isp1362_hc_stop(hcd); + return isp1362_hc_start(hcd); + } + if (status != -EINPROGRESS) { + return status; + } + spin_lock_irqsave(&isp1362_hcd->lock, flags); +#if MAX_ROOT_PORTS > 1 + port = isp1362_read_reg32(isp1362_hcd, HCRHDESCA) & RH_A_NDP; +#else + port = isp1362_read_reg32(isp1362_hcd, HCRHDESCA) & RH_A_NDP; + if(port == 0) + port = 0; + else + port = 1; +#endif + while (port--) { + u32 stat = isp1362_read_reg32(isp1362_hcd, HCRHPORT1 + port); + + /* force global, not selective, resume */ + if (!(stat & RH_PS_PSS)) { + DBG(0, "%s: Not Resuming RH port %d\n", __FUNCTION__, port); + continue; + } + DBG(0, "%s: Resuming RH port %d\n", __FUNCTION__, port); + isp1362_write_reg32(isp1362_hcd, HCRHPORT1 + port, RH_PS_POCI); + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + /* Some controllers (lucent) need extra-long delays */ + hcd->state = HC_STATE_RESUMING; + mdelay(20 /* usb 11.5.1.10 */ + 15); + + isp1362_hcd->hc_control = OHCI_USB_OPER; + if (hcd->can_wakeup) { + isp1362_hcd->hc_control |= OHCI_CTRL_RWC; + } + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_show_reg(isp1362_hcd, HCCONTROL); + isp1362_write_reg32(isp1362_hcd, HCCONTROL, isp1362_hcd->hc_control); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + /* TRSMRCY */ + msleep(10); + + /* keep it alive for ~5x suspend + resume costs */ + isp1362_hcd->next_statechange = jiffies + msecs_to_jiffies(250); + + hcd->self.root_hub->dev.power.power_state = PMSG_ON; + hcd->state = HC_STATE_RUNNING; + return 0; +} + +static void isp1362_rh_resume(void *_hcd) +{ + struct usb_hcd *hcd = _hcd; + + INFO("%s: \n", __FUNCTION__); + + usb_resume_device(hcd->self.root_hub); +} +#else +static void isp1362_rh_resume(void *_hcd) +{ + INFO("rh_resume ??\n"); +} + +#define isp1362_hub_suspend NULL +#define isp1362_hub_resume NULL +#endif + +/*-------------------------------------------------------------------------*/ + +#ifdef STUB_DEBUG_FILE + +static inline void create_debug_file(struct isp1362_hcd *isp1362_hcd) +{ +} +static inline void remove_debug_file(struct isp1362_hcd *isp1362_hcd) +{ +} + +#else + +#include +#include + +static void dump_irq(struct seq_file *s, char *label, u16 mask) +{ + seq_printf(s, "%-15s %04x%s%s%s%s%s%s\n", label, mask, + mask & HCuPINT_CLKRDY ? " clkrdy" : "", + mask & HCuPINT_SUSP ? " susp" : "", + mask & HCuPINT_OPR ? " opr" : "", + mask & HCuPINT_EOT ? " eot" : "", + mask & HCuPINT_ATL ? " atl" : "", + mask & HCuPINT_SOF ? " sof" : ""); +} + +static void dump_int(struct seq_file *s, char *label, u32 mask) +{ + seq_printf(s, "%-15s %08x%s%s%s%s%s%s%s\n", label, mask, + mask & OHCI_INTR_MIE ? " MIE" : "", + mask & OHCI_INTR_RHSC ? " rhsc" : "", + mask & OHCI_INTR_FNO ? " fno" : "", + mask & OHCI_INTR_UE ? " ue" : "", + mask & OHCI_INTR_RD ? " rd" : "", + mask & OHCI_INTR_SF ? " sof" : "", + mask & OHCI_INTR_SO ? " so" : ""); +} + +static void dump_ctrl(struct seq_file *s, char *label, u32 mask) +{ + seq_printf(s, "%-15s %08x%s%s%s\n", label, mask, + mask & OHCI_CTRL_RWC ? " rwc" : "", + mask & OHCI_CTRL_RWE ? " rwe" : "", + ({ + char *hcfs; + switch (mask & OHCI_CTRL_HCFS) { + case OHCI_USB_OPER: + hcfs = " oper"; + break; + case OHCI_USB_RESET: + hcfs = " reset"; + break; + case OHCI_USB_RESUME: + hcfs = " resume"; + break; + case OHCI_USB_SUSPEND: + hcfs = " suspend"; + break; + default: + hcfs = " ?"; + } + hcfs; + })); +} + +static void dump_regs(struct seq_file *s, struct isp1362_hcd *isp1362_hcd) +{ + seq_printf(s, "HCREVISION [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCREVISION), + isp1362_read_reg32(isp1362_hcd, HCREVISION)); + seq_printf(s, "HCCONTROL [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCCONTROL), + isp1362_read_reg32(isp1362_hcd, HCCONTROL)); + seq_printf(s, "HCCMDSTAT [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCCMDSTAT), + isp1362_read_reg32(isp1362_hcd, HCCMDSTAT)); + seq_printf(s, "HCINTSTAT [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCINTSTAT), + isp1362_read_reg32(isp1362_hcd, HCINTSTAT)); + seq_printf(s, "HCINTENB [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCINTENB), + isp1362_read_reg32(isp1362_hcd, HCINTENB)); + seq_printf(s, "HCFMINTVL [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCFMINTVL), + isp1362_read_reg32(isp1362_hcd, HCFMINTVL)); + seq_printf(s, "HCFMREM [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCFMREM), + isp1362_read_reg32(isp1362_hcd, HCFMREM)); + seq_printf(s, "HCFMNUM [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCFMNUM), + isp1362_read_reg32(isp1362_hcd, HCFMNUM)); + seq_printf(s, "HCLSTHRESH [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCLSTHRESH), + isp1362_read_reg32(isp1362_hcd, HCLSTHRESH)); + seq_printf(s, "HCRHDESCA [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCRHDESCA), + isp1362_read_reg32(isp1362_hcd, HCRHDESCA)); + seq_printf(s, "HCRHDESCB [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCRHDESCB), + isp1362_read_reg32(isp1362_hcd, HCRHDESCB)); + seq_printf(s, "HCRHSTATUS [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCRHSTATUS), + isp1362_read_reg32(isp1362_hcd, HCRHSTATUS)); + seq_printf(s, "HCRHPORT1 [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCRHPORT1), + isp1362_read_reg32(isp1362_hcd, HCRHPORT1)); + seq_printf(s, "HCRHPORT2 [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCRHPORT2), + isp1362_read_reg32(isp1362_hcd, HCRHPORT2)); + seq_printf(s, "\n"); + seq_printf(s, "HCHWCFG [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCHWCFG), + isp1362_read_reg16(isp1362_hcd, HCHWCFG)); + seq_printf(s, "HCDMACFG [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCDMACFG), + isp1362_read_reg16(isp1362_hcd, HCDMACFG)); + seq_printf(s, "HCXFERCTR [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCXFERCTR), + isp1362_read_reg16(isp1362_hcd, HCXFERCTR)); + seq_printf(s, "HCuPINT [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCuPINT), + isp1362_read_reg16(isp1362_hcd, HCuPINT)); + seq_printf(s, "HCuPINTENB [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), + isp1362_read_reg16(isp1362_hcd, HCuPINTENB)); + seq_printf(s, "HCCHIPID [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCCHIPID), + isp1362_read_reg16(isp1362_hcd, HCCHIPID)); + seq_printf(s, "HCSCRATCH [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCSCRATCH), + isp1362_read_reg16(isp1362_hcd, HCSCRATCH)); + seq_printf(s, "HCBUFSTAT [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCBUFSTAT), + isp1362_read_reg16(isp1362_hcd, HCBUFSTAT)); + seq_printf(s, "HCDIRADDR [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCDIRADDR), + isp1362_read_reg32(isp1362_hcd, HCDIRADDR)); +#if 0 + seq_printf(s, "HCDIRDATA [%02x] %04x\n", ISP1362_REG_NO(HCDIRDATA), + isp1362_read_reg16(isp1362_hcd, HCDIRDATA)); +#endif + seq_printf(s, "HCISTLBUFSZ[%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCISTLBUFSZ), + isp1362_read_reg16(isp1362_hcd, HCISTLBUFSZ)); + seq_printf(s, "HCISTLRATE [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCISTLRATE), + isp1362_read_reg16(isp1362_hcd, HCISTLRATE)); + seq_printf(s, "\n"); + seq_printf(s, "HCINTLBUFSZ[%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCINTLBUFSZ), + isp1362_read_reg16(isp1362_hcd, HCINTLBUFSZ)); + seq_printf(s, "HCINTLBLKSZ[%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCINTLBLKSZ), + isp1362_read_reg16(isp1362_hcd, HCINTLBLKSZ)); + seq_printf(s, "HCINTLDONE [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCINTLDONE), + isp1362_read_reg32(isp1362_hcd, HCINTLDONE)); + seq_printf(s, "HCINTLSKIP [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCINTLSKIP), + isp1362_read_reg32(isp1362_hcd, HCINTLSKIP)); + seq_printf(s, "HCINTLLAST [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCINTLLAST), + isp1362_read_reg32(isp1362_hcd, HCINTLLAST)); + seq_printf(s, "HCINTLCURR [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCINTLCURR), + isp1362_read_reg16(isp1362_hcd, HCINTLCURR)); + seq_printf(s, "\n"); + seq_printf(s, "HCATLBUFSZ [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCATLBUFSZ), + isp1362_read_reg16(isp1362_hcd, HCATLBUFSZ)); + seq_printf(s, "HCATLBLKSZ [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCATLBLKSZ), + isp1362_read_reg16(isp1362_hcd, HCATLBLKSZ)); +#if 0 + seq_printf(s, "HCATLDONE [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCATLDONE), + isp1362_read_reg32(isp1362_hcd, HCATLDONE)); +#endif + seq_printf(s, "HCATLSKIP [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCATLSKIP), + isp1362_read_reg32(isp1362_hcd, HCATLSKIP)); + seq_printf(s, "HCATLLAST [%02x] %08x\n", ISP1362_REG_NO(ISP1362_REG_HCATLLAST), + isp1362_read_reg32(isp1362_hcd, HCATLLAST)); + seq_printf(s, "HCATLCURR [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCATLCURR), + isp1362_read_reg16(isp1362_hcd, HCATLCURR)); + seq_printf(s, "\n"); + seq_printf(s, "HCATLDTC [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCATLDTC), + isp1362_read_reg16(isp1362_hcd, HCATLDTC)); + seq_printf(s, "HCATLDTCTO [%02x] %04x\n", ISP1362_REG_NO(ISP1362_REG_HCATLDTCTO), + isp1362_read_reg16(isp1362_hcd, HCATLDTCTO)); +} + +static int proc_isp1362_show(struct seq_file *s, void *unused) +{ + struct isp1362_hcd *isp1362_hcd = s->private; + struct isp1362_ep *ep; + int i; + + seq_printf(s, "%s\n%s version %s\n", + isp1362_hcd_to_hcd(isp1362_hcd)->product_desc, hcd_name, DRIVER_VERSION); + + /* collect statistics to help estimate potential win for + * DMA engines that care about alignment (PXA) + */ + seq_printf(s, "alignment: 16b/%ld 8b/%ld 4b/%ld 2b/%ld 1b/%ld\n", + isp1362_hcd->stat16, isp1362_hcd->stat8, isp1362_hcd->stat4, + isp1362_hcd->stat2, isp1362_hcd->stat1); + seq_printf(s, "max # ptds in ATL fifo: %d\n", isp1362_hcd->atl_queue.stat_maxptds); + seq_printf(s, "max # ptds in INTL fifo: %d\n", isp1362_hcd->intl_queue.stat_maxptds); + seq_printf(s, "max # ptds in ISTL fifo: %d\n", + max(isp1362_hcd->istl_queue[0].stat_maxptds, + isp1362_hcd->istl_queue[1].stat_maxptds)); + + // FIXME: don't show the following in suspended state + spin_lock_irq(&isp1362_hcd->lock); + + dump_irq(s, "hc_irq_enable", isp1362_read_reg16(isp1362_hcd, HCuPINTENB)); + dump_irq(s, "hc_irq_status", isp1362_read_reg16(isp1362_hcd, HCuPINT)); + dump_int(s, "ohci_int_enable", isp1362_read_reg32(isp1362_hcd, HCINTENB)); + dump_int(s, "ohci_int_status", isp1362_read_reg32(isp1362_hcd, HCINTSTAT)); + dump_ctrl(s, "ohci_control", isp1362_read_reg32(isp1362_hcd, HCCONTROL)); + + for (i = 0; i < NUM_ISP1362_IRQS; i++) { + if (isp1362_hcd->irq_stat[i]) { + seq_printf(s, "%-15s: %d\n", + ISP1362_INT_NAME(i), isp1362_hcd->irq_stat[i]); + } + } + + dump_regs(s, isp1362_hcd); + list_for_each_entry(ep, &isp1362_hcd->async, schedule) { + struct urb *urb; + + seq_printf(s, "%p, ep%d%s, maxpacket %d:\n", ep, ep->epnum, + ({ + char *s; + switch (ep->nextpid) { + case USB_PID_IN: + s = "in"; + break; + case USB_PID_OUT: + s = "out"; + break; + case USB_PID_SETUP: + s = "setup"; + break; + case USB_PID_ACK: + s = "status"; + break; + default: + s = "?"; + break; + }; + s;}), ep->maxpacket) ; + list_for_each_entry(urb, &ep->hep->urb_list, urb_list) { + seq_printf(s, " urb%p, %d/%d\n", urb, + urb->actual_length, + urb->transfer_buffer_length); + } + } + if (!list_empty(&isp1362_hcd->async)) { + seq_printf(s, "\n"); + } + dump_ptd_queue(&isp1362_hcd->atl_queue); + + seq_printf(s, "periodic size= %d\n", PERIODIC_SIZE); + + list_for_each_entry(ep, &isp1362_hcd->periodic, schedule) { + seq_printf(s, "branch:%2d load:%3d PTD[%d] $%04x:\n", ep->branch, + isp1362_hcd->load[ep->branch], ep->ptd_index, ep->ptd_offset); + + seq_printf(s, " %d/%p (%sdev%d ep%d%s max %d)\n", + ep->interval, ep, + (ep->udev->speed == USB_SPEED_FULL) ? "" : "ls ", + ep->udev->devnum, ep->epnum, + (ep->epnum == 0) ? "" : + ((ep->nextpid == USB_PID_IN) ? + "in" : "out"), ep->maxpacket); + } + dump_ptd_queue(&isp1362_hcd->intl_queue); + + seq_printf(s, "ISO:\n"); + + list_for_each_entry(ep, &isp1362_hcd->isoc, schedule) { + seq_printf(s, " %d/%p (%sdev%d ep%d%s max %d)\n", + ep->interval, ep, + (ep->udev->speed == USB_SPEED_FULL) ? "" : "ls ", + ep->udev->devnum, ep->epnum, + (ep->epnum == 0) ? "" : + ((ep->nextpid == USB_PID_IN) ? + "in" : "out"), ep->maxpacket); + } + + spin_unlock_irq(&isp1362_hcd->lock); + seq_printf(s, "\n"); + + return 0; +} + +static int proc_isp1362_open(struct inode *inode, struct file *file) +{ + return single_open(file, proc_isp1362_show, PDE(inode)->data); +} + +static struct file_operations proc_ops = { + .open = proc_isp1362_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +/* expect just one isp1362_hcd per system */ +static const char proc_filename[] = "driver/isp1362"; + +static void create_debug_file(struct isp1362_hcd *isp1362_hcd) +{ + struct proc_dir_entry *pde; + + pde = create_proc_entry(proc_filename, 0, NULL); + if (pde == NULL) { + WARN("%s: Failed to create debug file '%s'\n", __FUNCTION__, proc_filename); + return; + } + + pde->proc_fops = &proc_ops; + pde->data = isp1362_hcd; + isp1362_hcd->pde = pde; +} + +static void remove_debug_file(struct isp1362_hcd *isp1362_hcd) +{ + if (isp1362_hcd->pde) { + remove_proc_entry(proc_filename, 0); + } +} + +#endif + +/*-------------------------------------------------------------------------*/ + +static void isp1362_sw_reset(struct isp1362_hcd *isp1362_hcd) +{ + int tmp = 20; + unsigned long flags; + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + isp1362_write_reg16(isp1362_hcd, HCSWRES, HCSWRES_MAGIC); + isp1362_write_reg32(isp1362_hcd, HCCMDSTAT, OHCI_HCR); + while (--tmp) { + mdelay(1); + if (!(isp1362_read_reg32(isp1362_hcd, HCCMDSTAT) & OHCI_HCR)) { + break; + } + } + if (!tmp) { + ERR("Software reset timeout\n"); + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); +} + +static int isp1362_mem_config(struct usb_hcd *hcd) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long flags; + u32 total; + u16 istl_size = ISP1362_ISTL_BUFSIZE; + u16 intl_blksize = ISP1362_INTL_BLKSIZE + PTD_HEADER_SIZE; + u16 intl_size = ISP1362_INTL_BUFFERS * intl_blksize; + u16 atl_blksize = ISP1362_ATL_BLKSIZE + PTD_HEADER_SIZE; + u16 atl_buffers = (ISP1362_BUF_SIZE - (istl_size + intl_size)) / atl_blksize; + u16 atl_size; + int i; + + WARN_ON(istl_size & 3); + WARN_ON(atl_blksize & 3); + WARN_ON(intl_blksize & 3); + WARN_ON(atl_blksize < PTD_HEADER_SIZE); + WARN_ON(intl_blksize < PTD_HEADER_SIZE); + + BUG_ON((unsigned)ISP1362_INTL_BUFFERS > 32); + if (atl_buffers > 32) { + atl_buffers = 32; + } + atl_size = atl_buffers * atl_blksize; + total = atl_size + intl_size + istl_size; + dev_info(hcd->self.controller, "ISP1362 Memory usage:\n"); + dev_info(hcd->self.controller, " ISTL: 2 * %4d: %4d @ $%04x:$%04x\n", + istl_size / 2, istl_size, 0, istl_size / 2); + dev_info(hcd->self.controller, " INTL: %4d * (%3d+8): %4d @ $%04x\n", + ISP1362_INTL_BUFFERS, intl_blksize - PTD_HEADER_SIZE, + intl_size, istl_size); + dev_info(hcd->self.controller, " ATL : %4d * (%3d+8): %4d @ $%04x\n", + atl_buffers, atl_blksize - PTD_HEADER_SIZE, + atl_size, istl_size + intl_size); + dev_info(hcd->self.controller, " USED/FREE: %4d %4d\n", total, + ISP1362_BUF_SIZE - total); + + if (total > ISP1362_BUF_SIZE) { + dev_err(hcd->self.controller, "%s: Memory requested: %d, available %d\n", + __FUNCTION__, total, ISP1362_BUF_SIZE); + return -ENOMEM; + } + + total = istl_size + intl_size + atl_size; + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + for (i = 0; i < 2; i++) { + isp1362_hcd->istl_queue[i].buf_start = i * istl_size / 2, + isp1362_hcd->istl_queue[i].buf_size = istl_size / 2; + isp1362_hcd->istl_queue[i].blk_size = 4; + INIT_LIST_HEAD(&isp1362_hcd->istl_queue[i].active); + snprintf(isp1362_hcd->istl_queue[i].name, + sizeof(isp1362_hcd->istl_queue[i].name), "ISTL%d", i); + DBG(3, "%s: %5s buf $%04x %d\n", __FUNCTION__, + isp1362_hcd->istl_queue[i].name, + isp1362_hcd->istl_queue[i].buf_start, + isp1362_hcd->istl_queue[i].buf_size); + } + isp1362_write_reg16(isp1362_hcd, HCISTLBUFSZ, istl_size / 2); + + isp1362_hcd->intl_queue.buf_start = istl_size; + isp1362_hcd->intl_queue.buf_size = intl_size; + isp1362_hcd->intl_queue.buf_count = ISP1362_INTL_BUFFERS; + isp1362_hcd->intl_queue.blk_size = intl_blksize; + isp1362_hcd->intl_queue.buf_avail = isp1362_hcd->intl_queue.buf_count; + isp1362_hcd->intl_queue.skip_map = ~0; + INIT_LIST_HEAD(&isp1362_hcd->intl_queue.active); + + isp1362_write_reg16(isp1362_hcd, HCINTLBUFSZ, + isp1362_hcd->intl_queue.buf_size); + isp1362_write_reg16(isp1362_hcd, HCINTLBLKSZ, + isp1362_hcd->intl_queue.blk_size - PTD_HEADER_SIZE); + isp1362_write_reg32(isp1362_hcd, HCINTLSKIP, ~0); + isp1362_write_reg32(isp1362_hcd, HCINTLLAST, + 1 << (ISP1362_INTL_BUFFERS - 1)); + + isp1362_hcd->atl_queue.buf_start = istl_size + intl_size; + isp1362_hcd->atl_queue.buf_size = atl_size; + isp1362_hcd->atl_queue.buf_count = atl_buffers; + isp1362_hcd->atl_queue.blk_size = atl_blksize; + isp1362_hcd->atl_queue.buf_avail = isp1362_hcd->atl_queue.buf_count; + isp1362_hcd->atl_queue.skip_map = ~0; + INIT_LIST_HEAD(&isp1362_hcd->atl_queue.active); + + isp1362_write_reg16(isp1362_hcd, HCATLBUFSZ, + isp1362_hcd->atl_queue.buf_size); + isp1362_write_reg16(isp1362_hcd, HCATLBLKSZ, + isp1362_hcd->atl_queue.blk_size - PTD_HEADER_SIZE); + isp1362_write_reg32(isp1362_hcd, HCATLSKIP, ~0); + isp1362_write_reg32(isp1362_hcd, HCATLLAST, + 1 << (atl_buffers - 1)); + + snprintf(isp1362_hcd->atl_queue.name, + sizeof(isp1362_hcd->atl_queue.name), "ATL"); + snprintf(isp1362_hcd->intl_queue.name, + sizeof(isp1362_hcd->intl_queue.name), "INTL"); + DBG(3, "%s: %5s buf $%04x %2d * %4d = %4d\n", __FUNCTION__, + isp1362_hcd->intl_queue.name, + isp1362_hcd->intl_queue.buf_start, + ISP1362_INTL_BUFFERS, isp1362_hcd->intl_queue.blk_size, + isp1362_hcd->intl_queue.buf_size); + DBG(3, "%s: %5s buf $%04x %2d * %4d = %4d\n", __FUNCTION__, + isp1362_hcd->atl_queue.name, + isp1362_hcd->atl_queue.buf_start, + atl_buffers, isp1362_hcd->atl_queue.blk_size, + isp1362_hcd->atl_queue.buf_size); + + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + return 0; +} + +static int isp1362_hc_reset(struct usb_hcd *hcd) +{ + int ret = 0; + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long t; + unsigned long timeout = 20; + unsigned long flags; + int clkrdy = 0; + + INFO("%s:\n", __FUNCTION__); + + if (isp1362_hcd->board && isp1362_hcd->board->reset) { + isp1362_hcd->board->reset(hcd->self.controller, 1); + msleep(20); + if (isp1362_hcd->board->clock) { + isp1362_hcd->board->clock(hcd->self.controller, 1); + } + isp1362_hcd->board->reset(hcd->self.controller, 0); + } else { + isp1362_sw_reset(isp1362_hcd); + } + + // chip has been reset. First we need to see a clock + t = jiffies + msecs_to_jiffies(timeout); + while (!clkrdy && time_before_eq(jiffies, t)) { + spin_lock_irqsave(&isp1362_hcd->lock, flags); + clkrdy = isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_CLKRDY; + isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_CLKRDY); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + if (!clkrdy) { + msleep(4); + } + } + + if (!clkrdy) { + ERR("Clock not ready after %lums\n", timeout); + ret = -ENODEV; + } + return ret; +} + +static void isp1362_hc_stop(struct usb_hcd *hcd) +{ + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long flags; + u32 tmp; + + INFO("%s:\n", __FUNCTION__); + + del_timer_sync(&hcd->rh_timer); + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, 0); + + // Switch off power for all ports + tmp = isp1362_read_reg32(isp1362_hcd, HCRHDESCA); + tmp &= ~(RH_A_NPS | RH_A_PSM); + isp1362_write_reg32(isp1362_hcd, HCRHDESCA, tmp); + isp1362_write_reg32(isp1362_hcd, HCRHSTATUS, RH_HS_LPS); + + // Reset the chip + if (isp1362_hcd->board && isp1362_hcd->board->reset) { + isp1362_hcd->board->reset(hcd->self.controller, 1); + } else { + isp1362_sw_reset(isp1362_hcd); + } + if (isp1362_hcd->board && isp1362_hcd->board->clock) { + isp1362_hcd->board->clock(hcd->self.controller, 0); + } + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); +} + +#ifdef CHIP_BUFFER_TEST +static int isp1362_chip_test(struct isp1362_hcd *isp1362_hcd) +{ + int ret = 0; + u16 *ref; + unsigned long flags; + + ref = kmalloc(2 * ISP1362_BUF_SIZE, GFP_KERNEL); + if (ref) { + int offset; + u16 *tst = &ref[ISP1362_BUF_SIZE / 2]; + + for (offset = 0; offset < ISP1362_BUF_SIZE / 2; offset++) { + ref[offset] = ~offset; + tst[offset] = offset; + } + + for (offset = 0; offset < 4; offset++) { + int j; + + for (j = 0; j <= 8; j++) { + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_buffer(isp1362_hcd, (u8*)ref + offset, 0, j, 1); + udelay(500); + isp1362_read_buffer(isp1362_hcd, (u8*)tst + offset, 0, j, 1); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + if (memcmp(ref, tst, j)) { + ret = -ENODEV; + ERR("%s: memory check with %d byte offset %d failed\n", + __FUNCTION__, j, offset); + dump_data((u8*)ref + offset, j); + dump_data((u8*)tst + offset, j); + } + } + } + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_buffer(isp1362_hcd, ref, 0, ISP1362_BUF_SIZE, 0); + isp1362_read_buffer(isp1362_hcd, tst, 0, ISP1362_BUF_SIZE, 0); + if (memcmp(ref, tst, ISP1362_BUF_SIZE)) { + ERR("%s: memory check failed1\n", __FUNCTION__); + } + isp1362_read_buffer(isp1362_hcd, tst, 0, ISP1362_BUF_SIZE, 0); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + if (memcmp(ref, tst, ISP1362_BUF_SIZE)) { + ret = -ENODEV; + ERR("%s: memory check failed\n", __FUNCTION__); + dump_data((u8*)tst, ISP1362_BUF_SIZE / 2); + } + + for (offset = 0; offset < 256; offset++) { + int test_size = 0; + + yield(); + + memset(tst, 0, ISP1362_BUF_SIZE); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_buffer(isp1362_hcd, tst, 0, ISP1362_BUF_SIZE, 0); + isp1362_read_buffer(isp1362_hcd, tst, 0, ISP1362_BUF_SIZE, 0); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + if (memcmp(tst, tst + (ISP1362_BUF_SIZE / (2 * sizeof(*tst))), + ISP1362_BUF_SIZE / 2)) { + ERR("%s: Failed to clear buffer\n", __FUNCTION__); + dump_data((u8*)tst, ISP1362_BUF_SIZE); + break; + } + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_buffer(isp1362_hcd, ref, offset * 2, PTD_HEADER_SIZE, 1); + isp1362_write_buffer(isp1362_hcd, ref + PTD_HEADER_SIZE / sizeof(*ref), + offset * 2 + PTD_HEADER_SIZE, test_size, 1); + isp1362_read_buffer(isp1362_hcd, tst, offset * 2, + PTD_HEADER_SIZE + test_size, 1); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + if (memcmp(ref, tst, PTD_HEADER_SIZE + test_size)) { + dump_data(((u8*)ref) + offset, PTD_HEADER_SIZE + test_size); + dump_data((u8*)tst, PTD_HEADER_SIZE + test_size); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_read_buffer(isp1362_hcd, tst, offset * 2, + PTD_HEADER_SIZE + test_size, 1); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + if (memcmp(ref, tst, PTD_HEADER_SIZE + test_size)) { + ret = -ENODEV; + ERR("%s: memory check with offset %02x failed\n", + __FUNCTION__, offset); + break; + } + WARN("%s: memory check with offset %02x ok after second read\n", + __FUNCTION__, offset); + } + } + kfree(ref); + } + return ret; +} +#endif + +static int isp1362_hc_start(struct usb_hcd *hcd) +{ + int ret; + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + struct isp1362_platform_data *board = isp1362_hcd->board; + u16 hwcfg; + u16 chipid; + unsigned long flags; + + INFO("%s:\n", __FUNCTION__); + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + chipid = isp1362_read_reg16(isp1362_hcd, HCCHIPID); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + if ((chipid & HCCHIPID_MASK) != HCCHIPID_MAGIC) { + ERR("%s: Invalid chip ID %04x\n", __func__, chipid); + return -ENODEV; + } + +#ifdef CHIP_BUFFER_TEST + ret = isp1362_chip_test(isp1362_hcd); + if (ret) { + return -ENODEV; + } +#endif + spin_lock_irqsave(&isp1362_hcd->lock, flags); + // clear interrupt status and disable all interrupt sources + isp1362_write_reg16(isp1362_hcd, HCuPINT, 0x3ff); + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, 0); + + // HW conf + hwcfg = HCHWCFG_INT_ENABLE | HCHWCFG_DBWIDTH(1); + if (board->sel15Kres) { + hwcfg |= HCHWCFG_PULLDOWN_DS2 | + (MAX_ROOT_PORTS > 1) ? HCHWCFG_PULLDOWN_DS1 : 0; + } + if (board->clknotstop) { + hwcfg |= HCHWCFG_CLKNOTSTOP; + } + if (board->oc_enable) { + hwcfg |= HCHWCFG_ANALOG_OC; + } + if (board->int_act_high) { + hwcfg |= HCHWCFG_INT_POL; + } + if (board->int_edge_triggered) { + hwcfg |= HCHWCFG_INT_TRIGGER; + } + if (board->dreq_act_high) { + hwcfg |= HCHWCFG_DREQ_POL; + } + if (board->dack_act_high) { + hwcfg |= HCHWCFG_DACK_POL; + } + isp1362_write_reg16(isp1362_hcd, HCHWCFG, hwcfg); + isp1362_show_reg(isp1362_hcd, HCHWCFG); + isp1362_write_reg16(isp1362_hcd, HCDMACFG, 0); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + ret = isp1362_mem_config(hcd); + if (ret) { + return ret; + } + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + + // Root hub conf + isp1362_hcd->rhdesca = 0; + if (board->no_power_switching) { + isp1362_hcd->rhdesca |= RH_A_NPS; + } + if (board->power_switching_mode) { + isp1362_hcd->rhdesca |= RH_A_PSM; + } + if (board->potpg) { + isp1362_hcd->rhdesca |= (board->potpg << 24) & RH_A_POTPGT; + } else { + isp1362_hcd->rhdesca |= (25 << 24) & RH_A_POTPGT; + } + + isp1362_write_reg32(isp1362_hcd, HCRHDESCA, isp1362_hcd->rhdesca & ~RH_A_OCPM); + isp1362_write_reg32(isp1362_hcd, HCRHDESCA, isp1362_hcd->rhdesca | RH_A_OCPM); + isp1362_hcd->rhdesca = isp1362_read_reg32(isp1362_hcd, HCRHDESCA); + + isp1362_hcd->rhdescb = RH_B_PPCM; + isp1362_write_reg32(isp1362_hcd, HCRHDESCB, isp1362_hcd->rhdescb); + isp1362_hcd->rhdescb = isp1362_read_reg32(isp1362_hcd, HCRHDESCB); + + isp1362_read_reg32(isp1362_hcd, HCFMINTVL); + isp1362_write_reg32(isp1362_hcd, HCFMINTVL, (FSMP(FI) << 16) | FI); + isp1362_write_reg32(isp1362_hcd, HCLSTHRESH, LSTHRESH); + + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + hcd->state = HC_STATE_RUNNING; + + isp1362_hcd->hc_control = OHCI_USB_OPER; + if (board->remote_wakeup_connected) { + hcd->can_wakeup = 1; + isp1362_hcd->hc_control |= OHCI_CTRL_RWC; + } + + if (hcd->self.root_hub == NULL) + create_debug_file(isp1362_hcd); + + spin_lock_irqsave(&isp1362_hcd->lock, flags); + // Set up interrupts + isp1362_hcd->intenb = OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE; + isp1362_hcd->intenb |= OHCI_INTR_RD; + isp1362_hcd->irqenb = HCuPINT_OPR | HCuPINT_SUSP; + isp1362_write_reg32(isp1362_hcd, HCINTENB, isp1362_hcd->intenb); + isp1362_write_reg16(isp1362_hcd, HCuPINTENB, isp1362_hcd->irqenb); + + // Go operational + isp1362_write_reg32(isp1362_hcd, HCCONTROL, isp1362_hcd->hc_control); + // enable global power + isp1362_write_reg32(isp1362_hcd, HCRHSTATUS, RH_HS_LPSC | RH_HS_DRWE); + + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +static struct hc_driver isp1362_hc_driver = { + .description = hcd_name, + .product_desc = "ISP1362 Host Controller", + .hcd_priv_size = sizeof(struct isp1362_hcd), + + .irq = isp1362_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + .reset = isp1362_hc_reset, + .start = isp1362_hc_start, + .stop = isp1362_hc_stop, + + .urb_enqueue = isp1362_urb_enqueue, + .urb_dequeue = isp1362_urb_dequeue, + .endpoint_disable = isp1362_endpoint_disable, + + .get_frame_number = isp1362_get_frame, + + .hub_status_data = isp1362_hub_status_data, + .hub_control = isp1362_hub_control, + .hub_suspend = isp1362_hub_suspend, + .hub_resume = isp1362_hub_resume, +}; + +/*-------------------------------------------------------------------------*/ + +#define resource_len(r) (((r)->end - (r)->start) + 1) + +static int __init_or_module isp1362_remove(struct device *dev) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + struct platform_device *pdev; + struct resource *res; + + pdev = container_of(dev, struct platform_device, dev); + + remove_debug_file(isp1362_hcd); + DBG(0, "%s: Removing HCD\n", __FUNCTION__); + usb_remove_hcd(hcd); + + DBG(0, "%s: Unmapping data_reg @ %08x\n", __FUNCTION__, + (u32)isp1362_hcd->data_reg); + iounmap(isp1362_hcd->data_reg); + + DBG(0, "%s: Unmapping addr_reg @ %08x\n", __FUNCTION__, + (u32)isp1362_hcd->addr_reg); + iounmap(isp1362_hcd->addr_reg); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + DBG(0, "%s: release mem_region: %08lx\n", __FUNCTION__, res->start); + if (res) release_mem_region(res->start, resource_len(res)); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + DBG(0, "%s: release mem_region: %08lx\n", __FUNCTION__, res->start); + if (res) release_mem_region(res->start, resource_len(res)); + + DBG(0, "%s: put_hcd\n", __FUNCTION__); + usb_put_hcd(hcd); + DBG(0, "%s: Done\n", __FUNCTION__); + + return 0; +} + +static int __init isp1362_probe(struct device *dev) +{ + struct usb_hcd *hcd; + struct isp1362_hcd *isp1362_hcd; + struct platform_device *pdev; + struct resource *addr, *data; + void __iomem *addr_reg; + void __iomem *data_reg; + int irq; + int retval = 0; + + /* basic sanity checks first. board-specific init logic should + * have initialized this the three resources and probably board + * specific platform_data. we don't probe for IRQs, and do only + * minimal sanity checking. + */ + pdev = container_of(dev, struct platform_device, dev); + if (pdev->num_resources < 3) { + retval = -ENODEV; + goto err1; + } + + data = platform_get_resource(pdev, IORESOURCE_MEM, 0); + addr = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq = platform_get_irq(pdev, 0); + if (!addr || !data || irq < 0) { + retval = -ENODEV; + goto err1; + } + +#ifdef CONFIG_USB_HCD_DMA + if (dev->dma_mask) { + struct resource *dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + + if (!dma_res) { + retval = -ENODEV; + goto err1; + } + isp1362_hcd->data_dma = dma_res->start; + isp1362_hcd->max_dma_size = resource_len(dma_res); + } +#else + if (dev->dma_mask) { + DBG(1, "won't do DMA"); + retval = -ENODEV; + goto err1; + } +#endif + + if (!request_mem_region(addr->start, resource_len(addr), hcd_name)) { + retval = -EBUSY; + goto err1; + } + addr_reg = ioremap(addr->start, resource_len(addr)); + if (addr_reg == NULL) { + retval = -ENOMEM; + goto err2; + } + + if (!request_mem_region(data->start, resource_len(data), hcd_name)) { + retval = -EBUSY; + goto err3; + } + data_reg = ioremap(data->start, resource_len(data)); + if (data_reg == NULL) { + retval = -ENOMEM; + goto err4; + } + + /* allocate and initialize hcd */ + hcd = usb_create_hcd(&isp1362_hc_driver, dev, dev->bus_id); + if (!hcd) { + retval = -ENOMEM; + goto err5; + } + hcd->rsrc_start = data->start; + isp1362_hcd = hcd_to_isp1362_hcd(hcd); + isp1362_hcd->data_reg = data_reg; + isp1362_hcd->addr_reg = addr_reg; + + isp1362_hcd->next_statechange = jiffies; + spin_lock_init(&isp1362_hcd->lock); + INIT_LIST_HEAD(&isp1362_hcd->async); + INIT_LIST_HEAD(&isp1362_hcd->periodic); + INIT_LIST_HEAD(&isp1362_hcd->isoc); + INIT_LIST_HEAD(&isp1362_hcd->remove_list); + INIT_WORK(&isp1362_hcd->rh_resume, isp1362_rh_resume, hcd); + isp1362_hcd->board = dev->platform_data; +#ifdef USE_PLATFORM_DELAY + if (!isp1362_hcd->board->delay) { + dev_err(hcd->self.controller, "No platform delay function given\n"); + retval = -ENODEV; + goto err6; + } +#endif + +#ifdef CONFIG_ARM + if (isp1362_hcd->board) { + set_irq_type(irq, isp1362_hcd->board->int_act_high ? IRQT_RISING : IRQT_FALLING); + } +#endif + retval = usb_add_hcd(hcd, irq, SA_INTERRUPT); + if (retval != 0) { + goto err6; + } + + INFO("%s, irq %d\n", hcd->product_desc, irq); + + create_debug_file(isp1362_hcd); + + return 0; + + err6: + DBG(0, "%s: Freeing dev %08x\n", __FUNCTION__, (u32)isp1362_hcd); + usb_put_hcd(hcd); + err5: + DBG(0, "%s: Unmapping data_reg @ %08x\n", __FUNCTION__, (u32)data_reg); + iounmap(data_reg); + err4: + DBG(0, "%s: Releasing mem region %08lx\n", __FUNCTION__, data->start); + release_mem_region(data->start, resource_len(data)); + err3: + DBG(0, "%s: Unmapping addr_reg @ %08x\n", __FUNCTION__, (u32)addr_reg); + iounmap(addr_reg); + err2: + DBG(0, "%s: Releasing mem region %08lx\n", __FUNCTION__, addr->start); + release_mem_region(addr->start, resource_len(addr)); + err1: + printk("init error, %d\n", retval); + + return retval; +} + +#ifdef CONFIG_PM +static int isp1362_suspend(struct device *dev, u32 state, u32 phase) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long flags; + int retval = 0; + + INFO("%s: state %u phase %u\n", __FUNCTION__, state, phase); + + if (phase != SUSPEND_POWER_DOWN) { + DBG(0, "%s: Not suspending %d\n", __FUNCTION__, phase); + return retval; + } + DBG(0, "%s: Suspending device\n", __FUNCTION__); + + if (state <= PM_SUSPEND_MEM) { + DBG(0, "%s: Suspending root hub\n", __FUNCTION__); + retval = isp1362_hub_suspend(hcd); + } else { + DBG(0, "%s: Suspending RH ports\n", __FUNCTION__); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_reg32(isp1362_hcd, HCRHSTATUS, RH_HS_LPS); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + } + if (retval == 0) { + dev->power.power_state = state; + } + return retval; +} + +static int isp1362_resume(struct device *dev, u32 phase) +{ + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct isp1362_hcd *isp1362_hcd = hcd_to_isp1362_hcd(hcd); + unsigned long flags; + + INFO("%s: phase %u\n", __FUNCTION__, phase); + + if (phase != RESUME_POWER_ON) { + DBG(0, "%s: Not resuming: %d\n", __FUNCTION__, phase); + return 0; + } + DBG(0, "%s: Resuming: %d\n", __FUNCTION__, phase); + + if (dev->power.power_state > PM_SUSPEND_MEM || !hcd->can_wakeup) { + DBG(0, "%s: Resume RH ports\n", __FUNCTION__); + spin_lock_irqsave(&isp1362_hcd->lock, flags); + isp1362_write_reg32(isp1362_hcd, HCRHSTATUS, RH_HS_LPSC); + spin_unlock_irqrestore(&isp1362_hcd->lock, flags); + return 0; + } + + dev->power.power_state = PM_SUSPEND_ON; + + return isp1362_hub_resume(isp1362_hcd_to_hcd(isp1362_hcd)); +} +#else +#define isp1362_suspend NULL +#define isp1362_resume NULL +#endif + +static struct device_driver isp1362_driver = { + .name = (char *)hcd_name, + .bus = &platform_bus_type, + + .probe = isp1362_probe, + .remove = isp1362_remove, + + .suspend = isp1362_suspend, + .resume = isp1362_resume, +}; + +/*-------------------------------------------------------------------------*/ + +static int __init isp1362_init(void) +{ + if (usb_disabled()) { + return -ENODEV; + } + INFO("driver %s, %s\n", hcd_name, DRIVER_VERSION); + return driver_register(&isp1362_driver); +} + +module_init(isp1362_init); + +static void __exit isp1362_cleanup(void) +{ + driver_unregister(&isp1362_driver); +} + +module_exit(isp1362_cleanup); diff -Naur linux-2.6.14.6-20060127.org/drivers/usb/host/isp1362.h linux-2.6.14.6-20060127/drivers/usb/host/isp1362.h --- linux-2.6.14.6-20060127.org/drivers/usb/host/isp1362.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.14.6-20060127/drivers/usb/host/isp1362.h 2006-04-13 17:41:44.000000000 +0900 @@ -0,0 +1,1114 @@ +/* + * ISP1362 HCD (Host Controller Driver) for USB. + * + * COPYRIGHT (C) by L. Wassmann + * + * Portions: + * Copyright (C) 2005 Hayato Fujiwara (for M32R) + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * Platform specific compile time options + */ +#if defined(CONFIG_ARCH_KARO) +#include +#include +#include + +#define USE_32BIT 1 + +// These options are mutually exclusive +#define USE_PLATFORM_DELAY 1 +#define USE_NDELAY 0 +/* + * MAX_ROOT_PORTS: Number of downstream ports + * + * The chip has two USB ports, one of which can be configured as + * an USB device port, so the value of this constant is implementation + * specific. + */ +#define MAX_ROOT_PORTS 2 + +#define readsl(port, addr, count, endian) readsl(port, addr, count) +#define writesl(port, addr, count, endian) writesl(port, addr, count) +#define readsw(port, addr, count, endian) readsw(port, addr, count) +#define writesw(port, addr, count, endian) writesw(port, addr, count) + +#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) ||defined(CONFIG_PLAT_MAPPI3) || defined(CONFIG_PLAT_MAPPI2) + +#define USE_32BIT 0 + +// These options are mutually exclusive +#define USE_PLATFORM_DELAY 1 +#define USE_NDELAY 0 +#define USE_UDELAY 0 +/* + * MAX_ROOT_PORTS: Number of downstream ports + * + * The chip has two USB ports, one of which can be configured as + * an USB device port, so the value of this constant is implementation + * specific. + */ +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) +#define MAX_ROOT_PORTS 1 +#elif defined(CONFIG_PLAT_MAPPI3) || defined(CONFIG_PLAT_MAPPI2) +#define MAX_ROOT_PORTS 2 +#endif + +void readsw(volatile unsigned short *port, void *addr, unsigned long count, int endian) +{ + unsigned short tmp, *buf = addr; + + while (count--){ + if(endian){ + tmp = *(volatile unsigned short __force *)port; + *buf++ = cpu_to_le16(tmp); + }else{ + *buf++ = *(volatile unsigned short __force *)port; + } + } +} + +void writesw(volatile unsigned short *port, void *addr, unsigned long count, int endian) +{ + unsigned short tmp, *buf = addr; + + while (count--){ + if(endian){ + tmp = le16_to_cpu(*buf++); + *(volatile unsigned short __force *)port = tmp; + }else{ + *(volatile unsigned short __force *)port = *buf++; + } + } +} + +// insert platform specific definitions for other machines here +//#elif defined(CONFIG_ARCH_) +#else + +#warning No platform specific options defined, using defaults + +#define MAX_ROOT_PORTS 2 + +#define USE_32BIT 0 + +// These options are mutually exclusive +#define USE_PLATFORM_DELAY 0 +#define USE_NDELAY 0 + +#define readsl(port, addr, count, endian) readsl(port, addr, count) +#define writesl(port, addr, count, endian) writesl(port, addr, count) +#define readsw(port, addr, count, endian) readsw(port, addr, count) +#define writesw(port, addr, count, endian) writesw(port, addr, count) + +#endif + +/* ------------------------------------------------------------------------- */ + +#define USB_RESET_WIDTH 50 +#define MAX_XFER_SIZE 1023 + +// Buffer sizes +#define ISP1362_BUF_SIZE 4096 +#define ISP1362_ISTL_BUFSIZE 512 +#define ISP1362_INTL_BLKSIZE 64 +#define ISP1362_INTL_BUFFERS 16 +#define ISP1362_ATL_BLKSIZE 64 + +#define ISP1362_REG_WRITE_OFFSET 0x80 + +#ifdef DEBUG +typedef const unsigned int isp1362_reg_t; + +#define REG_WIDTH_16 0x000 +#define REG_WIDTH_32 0x100 +#define REG_WIDTH_MASK 0x100 +#define REG_NO_MASK 0x0ff + +#define REG_ACCESS_R 0x200 +#define REG_ACCESS_W 0x400 +#define REG_ACCESS_RW 0x600 +#define REG_ACCESS_MASK 0x600 + +#define ISP1362_REG_NO(r) ((r) & REG_NO_MASK) + +#define _BUG_ON(x) BUG_ON(x) +#define _WARN_ON(x) WARN_ON(x) + +#define ISP1362_REG(name,addr,width,rw) \ +static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw)) + +#define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W)) +#define REG_WIDTH_TEST(r,w) BUG_ON(((r) & REG_WIDTH_MASK) != (w)) +#else +typedef const unsigned char isp1362_reg_t; +#define ISP1362_REG_NO(r) (r) +#define _BUG_ON(x) do {} while (0) +#define _WARN_ON(x) do {} while (0) + +#define ISP1362_REG(name,addr,width,rw) \ +static isp1362_reg_t ISP1362_REG_##name = addr + +#define REG_ACCESS_TEST(r) do {} while (0) +#define REG_WIDTH_TEST(r,w) do {} while (0) +#endif + +// OHCI compatible registers +/* + * Note: Some of the ISP1362 'OHCI' registers implement only + * a subset of the bits defined in the OHCI spec. + * + * Bitmasks for the individual bits of these registers are defined in "ohci.h" + */ +ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R); +ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW); + +// Philips ISP1362 specific registers +ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW); +#define HCHWCFG_DISABLE_SUSPEND (1 << 15) +#define HCHWCFG_GLOBAL_PWRDOWN (1 << 14) +#define HCHWCFG_PULLDOWN_DS1 (1 << 13) +#define HCHWCFG_PULLDOWN_DS2 (1 << 12) +#define HCHWCFG_CLKNOTSTOP (1 << 11) +#define HCHWCFG_ANALOG_OC (1 << 10) +#define HCHWCFG_ONEINT (1 << 9) +#define HCHWCFG_DACK_MODE (1 << 8) +#define HCHWCFG_ONEDMA (1 << 7) +#define HCHWCFG_DACK_POL (1 << 6) +#define HCHWCFG_DREQ_POL (1 << 5) +#define HCHWCFG_DBWIDTH_MASK (0x03 << 3) +#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) +#define HCHWCFG_INT_POL (1 << 2) +#define HCHWCFG_INT_TRIGGER (1 << 1) +#define HCHWCFG_INT_ENABLE (1 << 0) + +ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW); +#define HCDMACFG_CTR_ENABLE (1 << 7) +#define HCDMACFG_BURST_LEN_MASK (0x03 << 5) +#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) +#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) +#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) +#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) +#define HCDMACFG_DMA_ENABLE (1 << 4) +#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) +#define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK) +#define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0) +#define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1) +#define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2) +#define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3) +#define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4) +#define HCDMACFG_DMA_RW_SELECT (1 << 0) + +ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW); + +ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW); +#define HCuPINT_SOF (1 << 0) +#define HCuPINT_ISTL0 (1 << 1) +#define HCuPINT_ISTL1 (1 << 2) +#define HCuPINT_EOT (1 << 3) +#define HCuPINT_OPR (1 << 4) +#define HCuPINT_SUSP (1 << 5) +#define HCuPINT_CLKRDY (1 << 6) +#define HCuPINT_INTL (1 << 7) +#define HCuPINT_ATL (1 << 8) +#define HCuPINT_OTG (1 << 9) + +ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW); +// same bit definitions apply as for HCuPINT + +ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R); +#define HCCHIPID_MASK 0xff00 +#define HCCHIPID_MAGIC 0x3600 + +ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW); + +ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W); +#define HCSWRES_MAGIC 0x00f6 + +ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW); +#define HCBUFSTAT_ISTL0_FULL (1 << 0) +#define HCBUFSTAT_ISTL1_FULL (1 << 1) +#define HCBUFSTAT_INTL_ACTIVE (1 << 2) +#define HCBUFSTAT_ATL_ACTIVE (1 << 3) +#define HCBUFSTAT_RESET_HWPP (1 << 4) +#define HCBUFSTAT_ISTL0_ACTIVE (1 << 5) +#define HCBUFSTAT_ISTL1_ACTIVE (1 << 6) +#define HCBUFSTAT_ISTL0_DONE (1 << 8) +#define HCBUFSTAT_ISTL1_DONE (1 << 9) +#define HCBUFSTAT_PAIRED_PTDPP (1 << 10) + +ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW); +#define HCDIRADDR_ADDR_MASK 0x0000ffff +#define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK) +#define HCDIRADDR_COUNT_MASK 0xffff0000 +#define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK) +ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW); + +ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW); + +ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R); +ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R); + +ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R); +ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW); +ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R); + +ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW); + + +ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R); +ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW); +ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW); + +// Philips transfer descriptor, cpu-endian +struct ptd { + u16 count; +#define PTD_COUNT_MSK (0x3ff << 0) +#define PTD_TOGGLE_MSK (1 << 10) +#define PTD_ACTIVE_MSK (1 << 11) +#define PTD_CC_MSK (0xf << 12) + u16 mps; +#define PTD_MPS_MSK (0x3ff << 0) +#define PTD_SPD_MSK (1 << 10) +#define PTD_LAST_MSK (1 << 11) +#define PTD_EP_MSK (0xf << 12) + u16 len; +#define PTD_LEN_MSK (0x3ff << 0) +#define PTD_DIR_MSK (3 << 10) +#define PTD_DIR_SETUP (0) +#define PTD_DIR_OUT (1) +#define PTD_DIR_IN (2) + u16 faddr; +#define PTD_FA_MSK (0x7f << 0) +// PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] +#define PTD_SF_ISO_MSK (0xff << 8) +#define PTD_SF_INT_MSK (0x1f << 8) +#define PTD_PR_MSK (0x07 << 13) +} __attribute__ ((packed, aligned(2))); +#define PTD_HEADER_SIZE sizeof(struct ptd) + +/* ------------------------------------------------------------------------- */ +/* Copied from ohci.h: */ +/* + * Hardware transfer status codes -- CC from PTD + */ +#define PTD_CC_NOERROR 0x00 +#define PTD_CC_CRC 0x01 +#define PTD_CC_BITSTUFFING 0x02 +#define PTD_CC_DATATOGGLEM 0x03 +#define PTD_CC_STALL 0x04 +#define PTD_DEVNOTRESP 0x05 +#define PTD_PIDCHECKFAIL 0x06 +#define PTD_UNEXPECTEDPID 0x07 +#define PTD_DATAOVERRUN 0x08 +#define PTD_DATAUNDERRUN 0x09 + /* 0x0A, 0x0B reserved for hardware */ +#define PTD_BUFFEROVERRUN 0x0C +#define PTD_BUFFERUNDERRUN 0x0D + /* 0x0E, 0x0F reserved for HCD */ +#define PTD_NOTACCESSED 0x0F + + +/* map OHCI TD status codes (CC) to errno values */ +static const int cc_to_error [16] = { + /* No Error */ 0, + /* CRC Error */ -EILSEQ, + /* Bit Stuff */ -EPROTO, + /* Data Togg */ -EILSEQ, + /* Stall */ -EPIPE, + /* DevNotResp */ -ETIMEDOUT, + /* PIDCheck */ -EPROTO, + /* UnExpPID */ -EPROTO, + /* DataOver */ -EOVERFLOW, + /* DataUnder */ -EREMOTEIO, + /* (for hw) */ -EIO, + /* (for hw) */ -EIO, + /* BufferOver */ -ECOMM, + /* BuffUnder */ -ENOSR, + /* (for HCD) */ -EALREADY, + /* (for HCD) */ -EALREADY +}; + + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +#define FI 0x2edf /* 12000 bits per frame (-1) */ +#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) +#define LSTHRESH 0x628 /* lowspeed bit threshold */ + +/* ------------------------------------------------------------------------- */ + +// PTD accessor macros. +#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0) +#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK) +#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10) +#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK) +#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11) +#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK) +#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12) +#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK) +#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0) +#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK) +#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10) +#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK) +#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11) +#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK) +#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12) +#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK) +#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0) +#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK) +#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10) +#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK) +#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0) +#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK) +#define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8) +#define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK) +#define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8) +#define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK) +#define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13) +#define PTD_PR(v) (((v) << 13) & PTD_PR_MSK) + +#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */ +#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE) + +struct isp1362_ep { + struct usb_host_endpoint *hep; + struct usb_device *udev; + + // philips transfer descriptor + struct ptd ptd; + + u8 maxpacket; + u8 epnum; + u8 nextpid; + u16 error_count; + u16 length; /* of current packet */ + s16 ptd_offset; /* buffer offset in ISP1362 where + PTD has been stored + (for access thru HCDIRDATA) */ + int ptd_index; + int num_ptds; + void *data; /* to databuf */ + // queue of active EPs (the ones transmitted to the chip) + struct list_head active; + + /* periodic schedule */ + u8 branch; + u16 interval; + u16 load; + u16 last_iso; + + /* async schedule */ + struct list_head schedule; /* list of all EPs that need processing */ + struct list_head remove_list; + int num_req; +}; + +struct isp1362_ep_queue { + struct list_head active; /* list of PTDs currently processed by HC */ + atomic_t finishing; + unsigned long buf_map; + unsigned long skip_map; + int free_ptd; + u16 buf_start; + u16 buf_size; + u16 blk_size; /* PTD buffer block size for ATL and INTL */ + u8 buf_count; + u8 buf_avail; + char name[16]; + + // for statistical tracking + u8 stat_maxptds; // Max # of ptds seen simultaneously in fifo + u8 ptd_count; // number of ptds submitted to this queue +}; + +struct isp1362_hcd { + spinlock_t lock; + void __iomem *addr_reg; + void __iomem *data_reg; + + struct isp1362_platform_data *board; + + struct proc_dir_entry *pde; + unsigned long stat1, stat2, stat4, stat8, stat16; + + // HC registers + u32 intenb; // "OHCI" interrupts + u16 irqenb; // uP interrupts + + // Root hub registers + u32 rhdesca; + u32 rhdescb; + u32 rhstatus; + u32 rhport[MAX_ROOT_PORTS]; + struct work_struct rh_resume; + unsigned long next_statechange; + + // HC control reg shadow copy + u32 hc_control; + + // async schedule: control, bulk + struct list_head async; + + // periodic schedule: int + u16 load[PERIODIC_SIZE]; + struct list_head periodic; + u16 fmindex; + + // periodic schedule: isochronous + struct list_head isoc; + int istl_flip:1; + int irq_active:1; + + // Schedules for the current frame + struct isp1362_ep_queue atl_queue; + struct isp1362_ep_queue intl_queue; + struct isp1362_ep_queue istl_queue[2]; + + // list of PTDs retrieved from HC + struct list_head remove_list; + enum { + ISP1362_INT_SOF, + ISP1362_INT_ISTL0, + ISP1362_INT_ISTL1, + ISP1362_INT_EOT, + ISP1362_INT_OPR, + ISP1362_INT_SUSP, + ISP1362_INT_CLKRDY, + ISP1362_INT_INTL, + ISP1362_INT_ATL, + ISP1362_INT_OTG, + NUM_ISP1362_IRQS + } IRQ_NAMES; + unsigned int irq_stat[NUM_ISP1362_IRQS]; + int req_serial; +}; + +static inline const char *ISP1362_INT_NAME(int n) { + const char *_name = "unknown"; + switch (n) { + case ISP1362_INT_SOF: + _name = "SOF"; + break; + case ISP1362_INT_ISTL0: + _name = "ISTL0"; + break; + case ISP1362_INT_ISTL1: + _name = "ISTL1"; + break; + case ISP1362_INT_EOT: + _name = "EOT"; + break; + case ISP1362_INT_OPR: + _name = "OPR"; + break; + case ISP1362_INT_SUSP: + _name = "SUSP"; + break; + case ISP1362_INT_CLKRDY: + _name = "CLKRDY"; + break; + case ISP1362_INT_INTL: + _name = "INTL"; + break; + case ISP1362_INT_ATL: + _name = "ATL"; + break; + case ISP1362_INT_OTG: + _name = "OTG"; + break; + } + return _name; +} + +static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr) +{ + unsigned p = (unsigned)ptr; + if (!(p & 0xf)) { + isp1362_hcd->stat16++; + } else if (!(p & 0x7)) { + isp1362_hcd->stat8++; + } else if (!(p & 0x3)) { + isp1362_hcd->stat4++; + } else if (!(p & 0x1)) { + isp1362_hcd->stat2++; + } else { + isp1362_hcd->stat1++; + } +} + +static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd) +{ + return (struct isp1362_hcd *) (hcd->hcd_priv); +} + +static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd) +{ + return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv); +} + +#define frame_before(f1,f2) ((s16)((u16)f1 - (u16)f2) < 0) + +/* + * ISP1362 HW Interface + */ + +#ifdef DEBUG +#define DBG(level, fmt...) do { \ + if (dbg_level > level) { \ + printk(KERN_DEBUG fmt); \ + } \ +} while (0) +#define _DBG(level, fmt...) do { \ + if (dbg_level > level) { \ + printk(fmt); \ + } \ +} while (0) +#else +#define DBG(fmt...) do {} while (0) +#define _DBG DBG +#endif + +#ifdef VERBOSE +# define VDBG(fmt...) DBG(3, fmt) +#else +# define VDBG(fmt...) do {} while (0) +#endif + +#ifdef REGISTERS +# define RDBG(fmt...) DBG(1, fmt) +#else +# define RDBG(fmt...) do {} while (0) +#endif + +#ifdef URB_TRACE +#define URB_DBG(fmt...) DBG(0, fmt) +#else +#define URB_DBG(fmt...) do {} while (0) +#endif + +#define ERR(fmt...) printk(KERN_ERR fmt) +#define WARN(fmt...) printk(KERN_WARNING fmt) +#define INFO(fmt...) printk(KERN_INFO fmt) + + +#if USE_PLATFORM_DELAY +#if USE_NDELAY +#error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously. +#endif +#define isp1362_delay(h,d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller,d) +#elif USE_NDELAY +#define isp1362_delay(h,d) ndelay(d) +#elif USE_UDELAY +#define isp1362_delay(h,d) udelay(d) +#else +#define isp1362_delay(h,d) do {} while (0) +#endif + +#define get_urb(ep) ({ \ + BUG_ON(list_empty(&ep->hep->urb_list)); \ + container_of(ep->hep->urb_list.next, struct urb, urb_list); \ +}) + +// basic access functions for ISP1362 chip registers +/* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure, + * that all register accesses are performed with interrupts disabled, since the interrupt + * handler has no way of restoring the previous state. + */ +static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg) +{ + //_BUG_ON((reg & ISP1362_REG_WRITE_OFFSET) && !(reg & REG_ACCESS_W)); + REG_ACCESS_TEST(reg); + _BUG_ON(!irqs_disabled()); + writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg); + isp1362_delay(isp1362_hcd, 1); +} + +static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val) +{ + _BUG_ON(!irqs_disabled()); + writew(val, isp1362_hcd->data_reg); +} + +static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd) +{ + u16 val; + + _BUG_ON(!irqs_disabled()); + val = readw(isp1362_hcd->data_reg); + + return val; +} + +static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val) +{ + _BUG_ON(!irqs_disabled()); +#if USE_32BIT + writel(val, isp1362_hcd->data_reg); +#else + writew((u16)val, isp1362_hcd->data_reg); + writew(val >> 16, isp1362_hcd->data_reg); +#endif +} + +static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd) +{ + u32 val; + + _BUG_ON(!irqs_disabled()); +#if USE_32BIT + val = readl(isp1362_hcd->data_reg); +#else + val = (u32)readw(isp1362_hcd->data_reg); + val |= (u32)readw(isp1362_hcd->data_reg) << 16; +#endif + return val; +} + +// use readsw/writesw to access the fifo whenever possible +// assume HCDIRDATA or XFERCTR & addr_reg have been set up +static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len, int endian) +{ + u8 *dp = buf; + u16 data; + + _BUG_ON(!irqs_disabled()); + if (!len) { + return; + } + RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __FUNCTION__, len, buf); +#if USE_32BIT + if (len >= 4) { + RDBG("%s: Using readsl for %d dwords\n", __FUNCTION__, len >> 2); + readsl(isp1362_hcd->data_reg, dp, len >> 2, endian); + dp += len & ~3; + len &= 3; + } +#endif + if (len >= 2) { + RDBG("%s: Using readsw for %d words\n", __FUNCTION__, len >> 1); + readsw(isp1362_hcd->data_reg, dp, len >> 1, endian); + dp += len & ~1; + len &= 1; + } + + BUG_ON(len & ~1); + if (len > 0) { + data = isp1362_read_data16(isp1362_hcd); + RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __FUNCTION__, + (u8)data, (u32)dp); + + *dp = (u8)data; + } +} + +static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len, int endian) +{ + u8 *dp = buf; + u16 data; + + _BUG_ON(!irqs_disabled()); + if (!len) { + return; + } + RDBG("%s: Writing %d byte to fifo from memory @%p\n", __FUNCTION__, len, buf); +#if USE_32BIT + if (len >= 4) { + RDBG("%s: Using writesl for %d dwords\n", __FUNCTION__, len >> 2); + writesl(isp1362_hcd->data_reg, dp, len >> 2, endian); + dp += len & ~3; + len &= 3; + } +#endif + if (len >= 2) { + RDBG("%s: Using writesw for %d words\n", __FUNCTION__, len >> 1); + writesw(isp1362_hcd->data_reg, dp, len >> 1, endian); + dp += len & ~1; + len &= 1; + } + + BUG_ON(len & ~1); + if (len > 0) { + // finally write any trailing byte; we don't need to care about the high byte of + // the last word written + data = (u16)*dp; + RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __FUNCTION__, + data, (u32)dp); + + isp1362_write_data16(isp1362_hcd, data); + } +} + +#define isp1362_read_reg16(d, r) ({ \ + u16 __v; \ + REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ + isp1362_write_addr(d, ISP1362_REG_##r); \ + __v = isp1362_read_data16(d); \ + RDBG("%s: Read %04x from %s[%02x]\n", __FUNCTION__, __v, #r, \ + ISP1362_REG_NO(ISP1362_REG_##r)); \ + __v; \ +}) + +#define isp1362_read_reg32(d, r) ({ \ + u32 __v; \ + REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ + isp1362_write_addr(d, ISP1362_REG_##r); \ + __v = isp1362_read_data32(d); \ + RDBG("%s: Read %08x from %s[%02x]\n", __FUNCTION__, __v, #r, \ + ISP1362_REG_NO(ISP1362_REG_##r)); \ + __v; \ +}) + +#define isp1362_write_reg16(d, r, v) { \ + REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ + isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ + isp1362_write_data16(d, (u16)(v)); \ + RDBG("%s: Wrote %04x to %s[%02x]\n", __FUNCTION__, (u16)(v), #r, \ + ISP1362_REG_NO(ISP1362_REG_##r)); \ +} + +#define isp1362_write_reg32(d, r, v) { \ + REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ + isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ + isp1362_write_data32(d, (u32)(v)); \ + RDBG("%s: Wrote %08x to %s[%02x]\n", __FUNCTION__, (u32)(v), #r, \ + ISP1362_REG_NO(ISP1362_REG_##r)); \ +} + +#define isp1362_set_mask16(d,r,m) { \ + u16 __v; \ + __v = isp1362_read_reg16(d, r); \ + if ((__v | m) != __v) { \ + isp1362_write_reg16(d, r, __v | m); \ + } \ +} + +#define isp1362_clr_mask16(d,r,m) { \ + u16 __v; \ + __v = isp1362_read_reg16(d, r); \ + if ((__v & ~m) != __v) { \ + isp1362_write_reg16(d, r, __v & ~m); \ + } \ +} + +#define isp1362_set_mask32(d,r,m) { \ + u32 __v; \ + __v = isp1362_read_reg32(d, r); \ + if ((__v | m) != __v) { \ + isp1362_write_reg32(d, r, __v | m); \ + } \ +} + +#define isp1362_clr_mask32(d,r,m) { \ + u32 __v; \ + __v = isp1362_read_reg32(d, r); \ + if ((__v & ~m) != __v) { \ + isp1362_write_reg32(d, r, __v & ~m); \ + } \ +} + +#ifdef DEBUG + +#define isp1362_show_reg(d,r) { \ + if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) { \ + DBG(0, "%-12s[%02x]: %08x\n", #r, \ + ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \ + } else { \ + DBG(0, "%-12s[%02x]: %04x\n", #r, \ + ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \ + } \ +} +#else +#define isp1362_show_reg(r,d) do {} while (0) +#endif + +static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd) +{ + isp1362_show_reg(isp1362_hcd, HCREVISION); + isp1362_show_reg(isp1362_hcd, HCCONTROL); + isp1362_show_reg(isp1362_hcd, HCCMDSTAT); + isp1362_show_reg(isp1362_hcd, HCINTSTAT); + isp1362_show_reg(isp1362_hcd, HCINTENB); + isp1362_show_reg(isp1362_hcd, HCFMINTVL); + isp1362_show_reg(isp1362_hcd, HCFMREM); + isp1362_show_reg(isp1362_hcd, HCFMNUM); + isp1362_show_reg(isp1362_hcd, HCLSTHRESH); + isp1362_show_reg(isp1362_hcd, HCRHDESCA); + isp1362_show_reg(isp1362_hcd, HCRHDESCB); + isp1362_show_reg(isp1362_hcd, HCRHSTATUS); + isp1362_show_reg(isp1362_hcd, HCRHPORT1); + isp1362_show_reg(isp1362_hcd, HCRHPORT2); + + isp1362_show_reg(isp1362_hcd, HCHWCFG); + isp1362_show_reg(isp1362_hcd, HCDMACFG); + isp1362_show_reg(isp1362_hcd, HCXFERCTR); + isp1362_show_reg(isp1362_hcd, HCuPINT); + + if (in_interrupt()) { + DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB", + ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb); + } else { + isp1362_show_reg(isp1362_hcd, HCuPINTENB); + } + isp1362_show_reg(isp1362_hcd, HCCHIPID); + isp1362_show_reg(isp1362_hcd, HCSCRATCH); + isp1362_show_reg(isp1362_hcd, HCBUFSTAT); + isp1362_show_reg(isp1362_hcd, HCDIRADDR); + // Access would advance fifo + //isp1362_show_reg(isp1362_hcd, HCDIRDATA); + isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ); + isp1362_show_reg(isp1362_hcd, HCISTLRATE); + isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ); + isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ); + isp1362_show_reg(isp1362_hcd, HCINTLDONE); + isp1362_show_reg(isp1362_hcd, HCINTLSKIP); + isp1362_show_reg(isp1362_hcd, HCINTLLAST); + isp1362_show_reg(isp1362_hcd, HCINTLCURR); + isp1362_show_reg(isp1362_hcd, HCATLBUFSZ); + isp1362_show_reg(isp1362_hcd, HCATLBLKSZ); + // only valid after ATL_DONE interrupt + //isp1362_show_reg(isp1362_hcd, HCATLDONE); + isp1362_show_reg(isp1362_hcd, HCATLSKIP); + isp1362_show_reg(isp1362_hcd, HCATLLAST); + isp1362_show_reg(isp1362_hcd, HCATLCURR); + isp1362_show_reg(isp1362_hcd, HCATLDTC); + isp1362_show_reg(isp1362_hcd, HCATLDTCTO); +} + +static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len) +{ + _BUG_ON(offset & 1); + _BUG_ON(offset >= ISP1362_BUF_SIZE); + _BUG_ON(len > ISP1362_BUF_SIZE); + _BUG_ON(offset + len > ISP1362_BUF_SIZE); + len = (len + 1) & ~1; + + isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE); + isp1362_write_reg32(isp1362_hcd, HCDIRADDR, + HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len)); +} + +static noinline void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len, int endian) +{ + _BUG_ON(offset & 1); + + isp1362_write_diraddr(isp1362_hcd, offset, len); + + DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %08x\n", __FUNCTION__, + len, offset, (u32)buf); + + isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); + _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); + + isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA); + + isp1362_read_fifo(isp1362_hcd, buf, len, endian); + + _WARN_ON(!(isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); + isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); + _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); +} + +static noinline void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len, int endian) +{ + _BUG_ON(offset & 1); + + isp1362_write_diraddr(isp1362_hcd, offset, len); + + DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %08x\n", __FUNCTION__, + len, offset, (u32)buf); + + isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); + _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); + + isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET); + isp1362_write_fifo(isp1362_hcd, buf, len, endian); + + _WARN_ON(!(isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); + isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); + _WARN_ON((isp1362_read_reg16(isp1362_hcd, HCuPINT) & HCuPINT_EOT)); +} + +static void __attribute__((unused)) dump_data(char *buf, int len) +{ + if (dbg_level > 0) { + int k; + int lf = 0; + + for (k = 0; k < len; ++k) { + if (!lf) DBG(0, "%04x:", k); + printk(" %02x", ((u8 *) buf)[k]); + lf = 1; + if (!k) { + continue; + } + if (k % 16 == 15) { + printk("\n"); + lf = 0; + continue; + } + if (k % 8 == 7) { + printk(" "); + } + if (k % 4 == 3) { + printk(" "); + } + } + if (lf) printk("\n"); + } +} + +#if defined(DEBUG) && defined(PTD_TRACE) + +static void dump_ptd(struct ptd *ptd) +{ + DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n", + container_of(ptd, struct isp1362_ep, ptd), + PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd), + PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), + PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd), + PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd)); + DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr); +} + +static void dump_ptd_out_data(struct ptd *ptd, u8 *buf) +{ + if (dbg_level > 0) { + if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) { + DBG(0, "--out->\n"); + dump_data(buf, PTD_GET_LEN(ptd)); + } + } +} + +static void dump_ptd_in_data(struct ptd *ptd, u8 *buf) +{ + if (dbg_level > 0) { + if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) { + DBG(0, "<--in--\n"); + dump_data(buf, PTD_GET_COUNT(ptd)); + } + DBG(0, "-----\n"); + } +} + +static void dump_ptd_queue(struct isp1362_ep_queue *epq) +{ + struct isp1362_ep *ep; + int dbg = dbg_level; + + dbg_level = 1; + list_for_each_entry(ep, &epq->active, active) { + dump_ptd(&ep->ptd); + dump_data(ep->data, ep->length); + } + dbg_level = dbg; +} +#else +#define dump_ptd(ptd) do {} while (0) +#define dump_ptd_in_data(ptd,buf) do {} while (0) +#define dump_ptd_out_data(ptd,buf) do {} while (0) +#define dump_ptd_data(ptd,buf) do {} while (0) +#define dump_ptd_queue(epq) do {} while (0) +#endif diff -Naur linux-2.6.14.6-20060127.org/include/asm-m32r/dma-mapping.h linux-2.6.14.6-20060127/include/asm-m32r/dma-mapping.h --- linux-2.6.14.6-20060127.org/include/asm-m32r/dma-mapping.h 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/include/asm-m32r/dma-mapping.h 2006-03-20 09:53:12.000000000 +0900 @@ -1,23 +1,7 @@ #ifndef _ASM_M32R_DMA_MAPPING_H #define _ASM_M32R_DMA_MAPPING_H -/* - * NOTE: Do not include - * Because it requires PCI stuffs, but current M32R don't provide these. - */ - -static inline void * -dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, - int flag) -{ - return (void *)NULL; -} - -static inline void -dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, - dma_addr_t dma_handle) -{ - return; -} +#include +#include #endif /* _ASM_M32R_DMA_MAPPING_H */ diff -Naur linux-2.6.14.6-20060127.org/include/asm-m32r/m32700ut/m32700ut_lcd.h linux-2.6.14.6-20060127/include/asm-m32r/m32700ut/m32700ut_lcd.h --- linux-2.6.14.6-20060127.org/include/asm-m32r/m32700ut/m32700ut_lcd.h 2006-01-27 19:00:32.000000000 +0900 +++ linux-2.6.14.6-20060127/include/asm-m32r/m32700ut/m32700ut_lcd.h 2006-04-18 17:10:08.000000000 +0900 @@ -96,6 +96,9 @@ #define ASNDSIOCR (M32700UT_LCD_BASE + 0x00301830) #define ASNDSIOSTS (M32700UT_LCD_BASE + 0x00301836) #define ASNDSIOINTCR (M32700UT_LCD_BASE + 0x00301838) +#define ASNDSIODMACR (M32700UT_LCD_BASE + 0x0030183a) +#define ASNDSIODMACR_TXCS (1<<4) +#define ASNDSIODMACR_RXCS (1<<5) #define ASNDSIOTXB_L (M32700UT_LCD_BASE + 0x0030183c) #define ASNDSIOTXB_R (M32700UT_LCD_BASE + 0x0030183e) #define ASNDSIORXB (M32700UT_LCD_BASE + 0x00301840) diff -Naur linux-2.6.14.6-20060127.org/include/asm-m32r/pci.h linux-2.6.14.6-20060127/include/asm-m32r/pci.h --- linux-2.6.14.6-20060127.org/include/asm-m32r/pci.h 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/include/asm-m32r/pci.h 2006-03-20 10:04:17.000000000 +0900 @@ -4,6 +4,7 @@ /* $Id$ */ #include +#include #define PCI_DMA_BUS_IS_PHYS (1) diff -Naur linux-2.6.14.6-20060127.org/include/asm-m32r/scatterlist.h linux-2.6.14.6-20060127/include/asm-m32r/scatterlist.h --- linux-2.6.14.6-20060127.org/include/asm-m32r/scatterlist.h 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/include/asm-m32r/scatterlist.h 2006-03-20 10:04:53.000000000 +0900 @@ -11,8 +11,12 @@ dma_addr_t dma_address; unsigned int length; + u32 dma_length; }; +#define sg_dma_address(sg) ((sg)->dma_address) +#define sg_dma_len(sg) ((sg)->dma_length) + #define ISA_DMA_THRESHOLD (0x1fffffff) #endif /* _ASM_M32R_SCATTERLIST_H */ diff -Naur linux-2.6.14.6-20060127.org/include/linux/usb_isp1362.h linux-2.6.14.6-20060127/include/linux/usb_isp1362.h --- linux-2.6.14.6-20060127.org/include/linux/usb_isp1362.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.14.6-20060127/include/linux/usb_isp1362.h 2006-03-20 10:14:27.000000000 +0900 @@ -0,0 +1,42 @@ + +/* + * board initialization code should put one of these into dev->platform_data + * and place the isp1362 onto platform_bus. + */ + +struct isp1362_platform_data { + // Enable internal pulldown resistors on downstream ports + unsigned sel15Kres:1; + // Clock cannot be stopped + unsigned clknotstop:1; + // On-chip overcurrent protection + unsigned oc_enable:1; + // INT output polarity + unsigned int_act_high:1; + // INT edge or level triggered + unsigned int_edge_triggered:1; + // DREQ output polarity + unsigned dreq_act_high:1; + // DACK input polarity + unsigned dack_act_high:1; + // chip can be resumed via H_WAKEUP pin + unsigned remote_wakeup_connected:1; + // Switch or not to switch (keep always powered) + unsigned no_power_switching:1; + // Ganged port power switching (0) or individual port power switching (1) + unsigned power_switching_mode:1; + // Given port_power, msec/2 after power on till power good + u8 potpg; + // Hardware reset set/clear + void (*reset) (struct device *dev, int set); + // Clock start/stop + void (*clock) (struct device *dev, int start); + /* Inter-io delay (ns). The chip is picky about access timings; it + expects at least: + 110ns delay between consecutive accesses to DATA_REG, + 300ns delay between access to ADDR_REG and DATA_REG (registers) + 462ns delay between access to ADDR_REG and DATA_REG (buffer memory) + WE MUST NOT be activated during these intervals (even without CS!) + */ + void (*delay) (struct device *dev, unsigned int delay); +}; diff -Naur linux-2.6.14.6-20060127.org/sound/oss/Kconfig linux-2.6.14.6-20060127/sound/oss/Kconfig --- linux-2.6.14.6-20060127.org/sound/oss/Kconfig 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/sound/oss/Kconfig 2006-03-19 23:29:23.000000000 +0900 @@ -136,6 +136,12 @@ slightly from OSS/Free, so PLEASE READ . +config SOUND_AK4524 + tristate "AK4524 CODEC chip driver" + depends on SOUND_PRIME && M32R + help + Say Y or M if you have a AK2524. + config SOUND_ESSSOLO1 tristate "ESS Technology Solo1" depends on SOUND_PRIME && PCI diff -Naur linux-2.6.14.6-20060127.org/sound/oss/Makefile linux-2.6.14.6-20060127/sound/oss/Makefile --- linux-2.6.14.6-20060127.org/sound/oss/Makefile 2006-01-08 11:15:24.000000000 +0900 +++ linux-2.6.14.6-20060127/sound/oss/Makefile 2006-03-19 23:30:14.000000000 +0900 @@ -63,6 +63,7 @@ endif obj-$(CONFIG_SOUND_ES1370) += es1370.o obj-$(CONFIG_SOUND_ES1371) += es1371.o ac97_codec.o +obj-$(CONFIG_SOUND_AK4524) += ak4524.o obj-$(CONFIG_SOUND_VRC5477) += nec_vrc5477.o ac97_codec.o obj-$(CONFIG_SOUND_AU1000) += au1000.o ac97_codec.o obj-$(CONFIG_SOUND_AU1550_AC97) += au1550_ac97.o ac97_codec.o diff -Naur linux-2.6.14.6-20060127.org/sound/oss/ak4524.c linux-2.6.14.6-20060127/sound/oss/ak4524.c --- linux-2.6.14.6-20060127.org/sound/oss/ak4524.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.6.14.6-20060127/sound/oss/ak4524.c 2006-04-17 15:07:52.000000000 +0900 @@ -0,0 +1,2041 @@ +/* + * AK4524 sound driver + * + * Copyright (C) 2004 Takeo Takahashi + * Copyright (C) 2004-2006 Hayato Fujiwara + * + * This program is based on: + * - audio driver for M32R refernce board. + * - es1370.c -- Ensoniq ES1370/Asahi Kasei AK4531 audio driver. + * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Supported devices: + * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible + * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible + * + * History: + * 2006-03-16: Hayato Fujiwara + * - port to linux-2.6 + * + * 2004-08-05: Takeo Takahashi + * - fix local_flush_cache_copyback_all() to flush only D-cache. + * - include to get CONFIG_PLAT_XXXX. + * - support 22050/11025/8820Hz rate in addition to 44100Hz. + * - bug fix: ioctl() DSP_GETODELAY, DSP_GETOSPACE. + * - bug fix: stop_dma() can not disable DMA translation. + * - add "swap_data" parameter experimentaly. + * - version v0.20 -> v0.30. + * + * 2004-07-05: Hayato Fujiwara + * - fix typo: CONFIG_PLAT_M32700 -> CONFIG_PLAT_M32700UT + * + * 2004-07-23: Mamoru Sakugawa + * - support OPSPUT board. + * + * 2004-07-13: Takeo Takahashi + * - first release v0.20 for M32700UT board. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* --------------------------------------------------------------------- */ + +#define OSS_DOCUMENTED_MIXER_SEMANTICS +#define DBG(x) {} +//#define DBG(x) {x} +//#define FLUSH_CACHE // now disabled due to noise. + +/* --------------------------------------------------------------------- */ +#define DMAEN 0x00ef8000 +#define DMAISTS 0x00ef8004 +#define DMAEDET 0x00ef8008 + +#define USE_DMA0 0 + +#if USE_DMA0 +#define DMAEN_DMSK 0x00008000 +#define DMAEN_DEN 0x00000080 +#define DMAEDET_DEDET 0x00008000 +#define DMAISTS_DISTS 0x00008000 +#define DMA_CR0 0x00ef8100 +#define DMA_CR1 0x00ef8104 +#define DMA_CSA 0x00ef8108 +#define DMA_RSA 0x00ef810c +#define DMA_CDA 0x00ef8110 +#define DMA_RDA 0x00ef8114 +#define DMA_CBCUT 0x00ef8118 +#define DMA_RBCUT 0x00ef811c +#define DMA_IRQ M32R_IRQ_DMA0 +#else +#define DMAEN_DMSK 0x00004000 +#define DMAEN_DEN 0x00000040 +#define DMAEDET_DEDET 0x00004000 +#define DMAISTS_DISTS 0x00004000 +#define DMA_CR0 0x00ef8200 +#define DMA_CR1 0x00ef8204 +#define DMA_CSA 0x00ef8208 +#define DMA_RSA 0x00ef820c +#define DMA_CDA 0x00ef8210 +#define DMA_RDA 0x00ef8214 +#define DMA_CBCUT 0x00ef8218 +#define DMA_RBCUT 0x00ef821c +#define DMA_IRQ M32R_IRQ_DMA1 +#endif + +#if defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) +#define DMA_CR0_REQSEL_DREQ0 0x1 +#elif defined(CONFIG_PLAT_M32700UT) +#define DMA_CR0_REQSEL_DREQ0 0x1e +#else +#error Unsupported Platform +#endif + + + +/* --------------------------------------------------------------------- */ +#define AK4524_MAGIC 0x12345678 + +#define DEFAULT_RATE 44100 + +#define CTRL_DAC_EN 0x00000020 /* enable DAC */ +#define CTRL_ADC_EN 0x00000010 /* enable ADC */ + +/* --------------------------------------------------------------------- */ +void start_AK4524(unsigned short format, unsigned long index,int mode, int iatt, int oatt ); + +/* --------------------------------------------------------------------- */ + +struct ak4524_state { + /* magic */ + unsigned int magic; + + /* list of ak4524 devices */ + struct list_head devs; + + /* the corresponding pci_dev structure */ + struct pci_dev *dev; + + /* soundcore stuff */ + int dev_audio; + int dev_mixer; + + /* hardware resources */ + unsigned long io; /* long for SPARC */ + unsigned int irq; + + /* mixer registers; there is no HW readback */ + struct { + unsigned short vol[10]; + unsigned int recsrc; + unsigned int modcnt; + unsigned short micpreamp; + unsigned int imix; + } mix; + + /* wave stuff */ + unsigned ctrl; + unsigned rate; + unsigned rfmt; /* record format */ + unsigned pfmt; /* play format */ + unsigned rchannels; + unsigned pchannels; + int oatt; + int iatt; + + spinlock_t lock; + struct semaphore open_sem; + mode_t open_mode; + wait_queue_head_t open_wait; + + struct dmabuf { + void *rawbuf; + dma_addr_t dmaaddr; + unsigned buforder; + unsigned numfrag; + unsigned fragshift; + unsigned hwptr, swptr; + unsigned total_bytes; + int count; + unsigned error; /* over/underrun */ + wait_queue_head_t wait; + /* redundant, but makes calculations easier */ + unsigned fragsize; + unsigned dmasize; + unsigned fragsamples; + /* OSS stuff */ + unsigned mapped:1; + unsigned ready:1; + unsigned endcleared:1; + unsigned enabled:1; + unsigned ossfragshift; + int ossmaxfrags; + unsigned subdivision; + } dma_dac, dma_adc; + + struct semaphore sem; +}; + +/* --------------------------------------------------------------------- */ + +static LIST_HEAD(devs); + +static int swap_data = 1; +module_param(swap_data, bool, 0); + +/* --------------------------------------------------------------------- */ +static void wrcodec(unsigned short reg, unsigned short data) +{ + unsigned long tmo = jiffies + HZ/10, j; + + do { + j = jiffies; + if(inw(ACNLSIOSTS) & 0x0001) { + outw(reg | data, ACNLSIOTXB); + DBG(printk("wrcodec: 0x%04x\n", reg | data);) + return; + } + schedule(); + } while ((signed)(tmo-j) > 0); + printk(KERN_ERR "ak4524: write to codec register timeout\n"); +} + +/* --------------------------------------------------------------------- */ +#define PIO_P4IEN 0x00ef1004 +#define PIO_P4DIR 0x00ef1014 +#define PIO_P4PDCR 0x00ef1028 +#define PIO_P4MOD 0x00ef1068 + +#define MAX_ATT 128 + +/******************************************* + PWM for MFT0,1,2 +*******************************************/ +const unsigned short PWMTBL[4][5] = { + { /* 44100Hz */ + 0, /* AKCLKCR used as XTI(512fs=22.5792MHz) */ + 7, /* MFT0CUT 1/16 MFT0 used as BICK(64fs=2.8224MHz) */ + 0, /* MFT0CMPRLD */ + 511, /* MFT2CUT 1/1024 MFT2 used as LRCK(fs=44.1kHz) */ + 0, /* MFT2CMPRLD */ + }, + { /* 22050Hz */ + 1, /* AKCLKCR used as XTI(512fs=11.2896MHz) */ + 15, /* MFT0CUT 1/32 MFT0 used as BICK(64fs=1.4112MHz) */ + 0, /* MFT0CMPRLD */ + 1023, /* MFT2CUT 1/2048 MFT2 used as LRCK(fs=22.05kHz) */ + 0, /* MFT2CMPRLD */ + }, + { /* 11025Hz */ + 3, /* AKCLKCR used as XTI(512fs=5.6448MHz) */ + 31, /* MFT0CUT 1/64 MFT0 used as BICK(64fs=705.6kHz) */ + 0, /* MFT0CMPRLD */ + 2047, /* MFT2CUT 1/4096 MFT2 used as LRCK(fs=11.025kHz) */ + 0, /* MFT2CMPRLD */ + }, + { /* 8820Hz */ + 4, /* AKCLKCR used as XTI(512fs=4.515840MHz)*/ + 39, /* MFT0CUT 1/80 MFT0 used as BICK(64fs=564.480kHz) */ + 0, /* MFT0CMPRLD */ + 2559, /* MFT2CUT 1/5120 MFT2 used as LRCK(fs=8.820kHz) */ + 0, /* MFT2CMPRLD */ + } +}; + +/* + * AK4524 Serial control I/F + */ +#define SUBADDR0 0xA000 /* SubAddr:0 for Power-Down */ +#define SUBADDR1 0xA100 /* SubAddr:1 for Reset */ +#define SUBADDR2 0xA200 /* SubAddr:2 for Clock & Format */ +#define SUBADDR3 0xA300 /* SubAddr:3 for SMUTE & DEM */ +#define SUBADDR4 0xA400 /* SubAddr:4 for ADC ATT-Lch */ +#define SUBADDR5 0xA500 /* SubAddr:5 for ADC ATT-Rch */ +#define SUBADDR6 0xA600 /* SubAddr:6 for DAC ATT-Lch */ +#define SUBADDR7 0xA700 /* SubAddr:7 for DAC ATT-Rch */ + +#define SUBADDR0_INIT 0x0007 /* SUBADDR0:PowerDownControl[PWVR:1,PWAD:1,PWDA:1] */ +#define SUBADDR1_INIT 0x0000 /* SUBADDR1:ResetControl[RSTAD:0,RSTDA:0] */ +#define SUBADDR1_RSTCLR 0x0003 /* SUBADDR1:ResetControl[RSTAD:1,RSTDA:1] */ +#define SUBADDR2_INIT 0x0004 /* SUBADDR2:DIF2-0:000(Mode0),CMOD,CKS2-1:001(512fs),DFS1-0:00(Normal) */ +#define SUBADDR3_INIT 0x0019 /* SUBADDR3:SMUTE:0(OFF),ZCEI:1,ZTM1-0:10,DEM1-0:01(OFF) */ + +static void wait_time(long times,long value) +{ + volatile long i, t; + for (i = 0; i < times; i++) + t = value; +} + +static void wrcodec_OATT(unsigned char volume) +{ + wrcodec(SUBADDR6, (unsigned short)volume); /* DAC Lch */ + wait_time(100, 0); + wrcodec(SUBADDR7, (unsigned short)volume); /* DAC Rch */ +} + +static void wrcodec_IATT(unsigned char volume) +{ + wrcodec(SUBADDR4, (unsigned short)volume); /* DAC Lch */ + wait_time(100, 0); + wrcodec(SUBADDR5, (unsigned short)volume); /* DAC Rch */ +} + +void init_port(void) +{ + unsigned char reg8; + unsigned short reg16; + + DBG(printk("init_port:\n");) + + /* P44 */ + reg8 = inb(PIO_P4DIR); + reg8 &= ~0x08; + outb(reg8, PIO_P4DIR); // input mode + + reg16 = inw(PIO_P4PDCR); + reg16 &= ~0x00c0; // clear PAD44 + reg16 |= 0x0080; // pull-up + outw(reg16, PIO_P4PDCR); + + reg16 = inw(PIO_P4MOD); + reg16 &= ~0x00c0; // clear MD44 + reg16 |= 0x0040; // DREQ0 + outw(reg16, PIO_P4MOD); + + reg8 = inb(PIO_P4IEN); + reg8 |= 0x08; // enable input + outb(reg8, PIO_P4IEN); +} + +void init_audio(void) +{ + DBG(printk("init_audio:\n");) + + /* + * + * initialize serial port for communication with AK4524. + */ + outw(0x0000, ACNLSIOCR); /* disable all */ + while(inw(ACNLSIOSTS) & 0x0100) ; /* wait for end of sending */ + /* 3,763,200bps (ref.M3A-2139:4,233,600bps ) (AK4524 Max:5MHz) */ + outw(5, ACNLSIOBAUR); + outw(0x0000, ACNLSIOINTCR); /* disable interrupt */ + outw(0x0001, ACNLSIOCR); /* enable output */ +} + +#ifdef FLUSH_CACHE +/* Cache Control Register */ +#ifdef MCCR +#undef MCCR +#endif +#define MCCR ((volatile unsigned long*)0xfffffffc) +#define MCCR_CC (1UL << 7) /* Cache mode modify bit */ +#define MCCR_IIV (1UL << 6) /* I-cache invalidate */ +#define MCCR_DIV (1UL << 5) /* D-cache invalidate */ +#define MCCR_DCB (1UL << 4) /* D-cache copy back */ +#define MCCR_ICM (1UL << 1) /* I-cache mode [0:off,1:on] */ +#define MCCR_DCM (1UL << 0) /* D-cache mode [0:off,1:on] */ +#define MCCR_ICACHE_INV (MCCR_CC|MCCR_IIV) +#define MCCR_DCACHE_CB (MCCR_CC|MCCR_DCB) +#define MCCR_DCACHE_CBINV (MCCR_CC|MCCR_DIV|MCCR_DCB) +#define CHECK_MCCR(mccr) (mccr = *MCCR) + +static void local_flush_cache_copyback_all(void) +{ + /* Copyback D-cache */ + *MCCR = MCCR_DCACHE_CB; +} +#endif + +void stop_dma(struct ak4524_state *s) +{ + unsigned long reg; + + reg = inl(DMAEN); + reg &= ~DMAEN_DEN; + reg |= DMAEN_DMSK; + outl(reg, DMAEN); /* disable DMA */ + reg = inl(DMAEDET); + reg |= DMAEDET_DEDET; + outl(reg, DMAEDET); /* clear detect flag */ +} + +void check_dma(struct ak4524_state *s) +{ + DBG(printk("DMA_CBCUT=%d\n", (int)inl(DMA_CBCUT));) +} + +void start_dma_dac(struct ak4524_state *s) +{ + unsigned int next_hwptr; + unsigned long reg; + + DBG(printk("start_dma_dac:\n");) + /* SDRAM -> PLD */ + /* DREQ:0, -, SZSEL:10(word), + * -, MDSEL:0, -, DIRQ:1, + * DSEL:0(1operand), OPSEL: 000(1datum), + * ALSEL:0(L), BRLOD:1, SRLOD:1, DRLOD:1 + * SAMOD:01(+), DAMOD:00 + * -, -, TDIR:11(external->external) + * DSE:01 , - + * REQSEL: 11110 DREQ0 + */ + /* 0-10 -0-1 0000 0111 0100 0011 0101 1110 */ + + outl(0x21074340 | DMA_CR0_REQSEL_DREQ0, DMA_CR0); + + /* ECLR: not to clear DEN1 */ + outl(0x00000000, DMA_CR1); + + /* address registers */ + outl(s->dma_dac.dmaaddr + s->dma_dac.hwptr, DMA_CSA); + next_hwptr = (s->dma_dac.hwptr + s->dma_dac.fragsize) % s->dma_dac.dmasize; + outl(s->dma_dac.dmaaddr + next_hwptr, DMA_RSA); + outl(ASNDSIOTXB_L, DMA_CDA); + outl(ASNDSIOTXB_L, DMA_RDA); + outl(s->dma_dac.fragsize, DMA_CBCUT); + outl(s->dma_dac.fragsize, DMA_RBCUT); + DBG(printk("dmaaddr: 0x%x - 0x%x\n", s->dma_dac.dmaaddr, s->dma_dac.dmaaddr + s->dma_dac.dmasize);) + DBG(printk("DMA_CSA = 0x%lx\n", inl(DMA_CSA));) + DBG(printk("DMA_RSA = 0x%lx\n", inl(DMA_RSA));) + DBG(printk("DMA_CDA = 0x%lx\n", inl(DMA_CDA));) + DBG(printk("DMA_RDA = 0x%lx\n", inl(DMA_RDA));) + DBG(printk("DMA_CBCUT = 0x%lx\n", inl(DMA_CBCUT));) + DBG(printk("DMA_RBCUT = 0x%lx\n", inl(DMA_RBCUT));) + DBG(printk("s->dma_dac.dmaaddr = 0x%x\n", (int)(s->dma_dac.dmaaddr));) + DBG(printk("s->dma_dac.fragsize = %d\n", s->dma_dac.fragsize);) + + reg = inl(DMAEN); + reg |= (DMAEN_DMSK | DMAEN_DEN); + outl(reg, DMAEN); /* enable DMA */ + + /* write neutral data to kick an interrupt */ + outl(0x0, ASNDSIOTXB_L); +} + +void start_dma_adc(struct ak4524_state *s) +{ + unsigned int next_hwptr; + unsigned long reg; + + DBG(printk("start_dma_adc:\n");) + /* PLD -> SDRAM */ + /* DREQ:0, -, SZSEL:01(half-word), + * -, MDSEL:0, -, DIRQ:1, + * DSEL:0(1operand), OPSEL: 000(1datum), + * ALSEL:0(L), BRLOD:1, SRLOD:1, DRLOD:1 + * SAMOD:00, DAMOD:01(+) + * -, -, TDIR:11(external->external) + * DSE:01 , - + * REQSEL: 11110 DREQ0 + */ + /* 0-01 -0-1 0000 0111 0001 --11 01-1 1110 */ + outl(0x1107135e, DMA_CR0); + + /* ECLR: not to clear DEN1 */ + outl(0x00000000, DMA_CR1); + + /* address registers */ + outl(ASNDSIORXB, DMA_CSA); + outl(ASNDSIORXB, DMA_RSA); + outl(s->dma_adc.dmaaddr + s->dma_adc.hwptr, DMA_CDA); + next_hwptr = (s->dma_adc.hwptr + s->dma_adc.fragsize) % s->dma_adc.dmasize; + outl(s->dma_adc.dmaaddr + next_hwptr, DMA_RDA); + outl(s->dma_adc.fragsize, DMA_CBCUT); + outl(s->dma_adc.fragsize, DMA_RBCUT); + DBG(printk("dmaaddr: 0x%x - 0x%x\n", s->dma_adc.dmaaddr, s->dma_adc.dmaaddr + s->dma_adc.dmasize);) + DBG(printk("DMA_CSA = 0x%lx\n", inl(DMA_CSA));) + DBG(printk("DMA_RSA = 0x%lx\n", inl(DMA_RSA));) + DBG(printk("DMA_CDA = 0x%lx\n", inl(DMA_CDA));) + DBG(printk("DMA_RDA = 0x%lx\n", inl(DMA_RDA));) + DBG(printk("DMA_CBCUT = 0x%lx\n", inl(DMA_CBCUT));) + DBG(printk("DMA_RBCUT = 0x%lx\n", inl(DMA_RBCUT));) + DBG(printk("s->dma_adc.dmaaddr = 0x%x\n", (int)(s->dma_adc.dmaaddr));) + DBG(printk("s->dma_adc.fragsize = %d\n", s->dma_adc.fragsize);) + + reg = inl(DMAEN); + reg |= (DMAEN_DMSK | DMAEN_DEN); + outl(reg, DMAEN); /* enable DMA */ +} + +/* + * format: format ID + * index: index of sampling freq + * mode: 0:play 1:record + */ +void start_AK4524(unsigned short format, unsigned long rate,int mode, int iatt, int oatt) +{ + int index; + + DBG(printk("start_AK4524\n");) + + switch (rate) { + case 44100: index = 0; break; + case 22050: index = 1; break; + case 11025: index = 2; break; + case 8820: index = 3; break; + default: index = 0; break; + } + + if(mode == 0) // play + outw(0, AUDMSCR); + else // record + outw(1, AUDMSCR); + + /* + * Initialize MTF + */ +#if 1 + outw(0xa000, AUDTCR); /* disable timer */ + wait_time(0x100, 10); +#endif + + /* set BICK count (count source = 45.1584MHz) */ + outw(PWMTBL[index][1], AUDT0CUT); + DBG(printk("PWMTBL[%d][1]=%d\n", (int)index,PWMTBL[index][1]);) + + /* set LRCK count (count source = 45.1584MHz) */ + outw(PWMTBL[index][3], AUDT2CUT); + DBG(printk("PWMTBL[%d][3]=%d\n", (int)index,PWMTBL[index][3]);) + +#if 1 + outw(0xa0a0, AUDTCR); /* enable timer */ + wait_time(0x1000, 10); +#endif + + /* stop serial port (ASNDSIO). */ +#if 0 + while ((inw(ASNDSIOSTS) & 0x0103) != 0x0003) ; /* wait for end */ + while ((inw(ASNDSIOSTS) & 0x0004) != 0) { + (void)inw(ASNDSIORXB); /* wait for end */ + } +#endif + outw(0x0000, ASNDSIOCR); /* disable sound sio */ + + /* Initialize serial port (ASNDSIO) to read/write sound data. */ + if(mode == 0) { // play + outw(0x0001, ASNDSIOINTCR); // enable TEMPIE + outw(ASNDSIODMACR_TXCS, ASNDSIODMACR); // enable DMA request + } else { // record + outw(0x0004, ASNDSIOINTCR); // enable RXIEN + outw(ASNDSIODMACR_RXCS, ASNDSIODMACR); // enable DMA request + } + + /* start XTI (by PLD) to reset */ + outw(PWMTBL[index][0], AUDXTICR); + DBG(printk("PWMTBL[%d][0]=%d\n", (int)index,PWMTBL[index][0]);) + wait_time(10, 0); + + /* + * initialize AK4524 registers + */ + wrcodec(SUBADDR2, SUBADDR2_INIT); + wait_time(0x1000, 10); + wrcodec(SUBADDR3, SUBADDR3_INIT | (0<<7)); /* D7:SMUTE(off) */ + wait_time(0x1000, 10); + wrcodec_OATT(oatt); /* set OATT */ + wait_time(0x1000, 10); + wrcodec(SUBADDR1, SUBADDR1_RSTCLR); + wait_time(0x1000, 10); + wrcodec_IATT(iatt); /* set IATT */ + wait_time(0x1000, 10); + wrcodec_OATT(oatt); /* set OATT again */ + wait_time(0x1000, 10); + + if (mode == 0) + outw(0x0001, ASNDSIOCR); /* enable */ + else + outw(0x0002, ASNDSIOCR); /* enable */ +} + +void stop_AK4524(void) +{ + + DBG(printk("stop_AK4524:\n");) + + /* D7:SMUTE(on) before power-down */ + //wrcodec(SUBADDR3, SUBADDR3_INIT | (1<<7)); + //wait_time(0x1000, 10); + + outw(0x0000, ASNDSIOINTCR); /* disable int. */ + outw(0x0000, ASNDSIOCR); /* disable data sio */ +} + +/* --------------------------------------------------------------------- */ + +static inline void stop_adc(struct ak4524_state *s) +{ + unsigned long flags; + + spin_lock_irqsave(&s->lock, flags); + s->ctrl &= ~CTRL_ADC_EN; + stop_dma(s); + spin_unlock_irqrestore(&s->lock, flags); +} + +static inline void stop_dac(struct ak4524_state *s) +{ + unsigned long flags; + + DBG(printk("stop_dac:\n");) + spin_lock_irqsave(&s->lock, flags); + s->ctrl &= ~CTRL_DAC_EN; + stop_dma(s); + spin_unlock_irqrestore(&s->lock, flags); +} + +static void start_dac(struct ak4524_state *s) +{ + unsigned long flags; + + //DBG(printk("start_dac:\n");) + spin_lock_irqsave(&s->lock, flags); + if (!(s->ctrl & CTRL_DAC_EN) && (s->dma_dac.mapped || s->dma_dac.count > 0) + && s->dma_dac.ready) { + s->ctrl |= CTRL_DAC_EN; + stop_dma(s); + start_dma_dac(s); + } + spin_unlock_irqrestore(&s->lock, flags); +} + +static void start_adc(struct ak4524_state *s) +{ + unsigned long flags; + //unsigned fragremain, fshift; + + DBG(printk("start_adc:\n");) + spin_lock_irqsave(&s->lock, flags); + DBG(printk("count=%d, dmasize=%d, fragsize=%d\n", s->dma_adc.count, s->dma_adc.dmasize, s->dma_adc.fragsize);) + if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize)) + && s->dma_adc.ready) { + s->ctrl |= CTRL_ADC_EN; + stop_dma(s); + start_dma_adc(s); + } + spin_unlock_irqrestore(&s->lock, flags); +} + +/* --------------------------------------------------------------------- */ + +#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT) // 17-12 = 5, 4KB*2^5 = 128KB +#define DEFAULT_FRAGSHIFT 15 + +static inline void dealloc_dmabuf(struct ak4524_state *s, struct dmabuf *db) +{ + //struct page *page, *pend; + + if (db->rawbuf) + kfree(db->rawbuf); + db->rawbuf = NULL; + db->mapped = db->ready = 0; +} + +static int prog_dmabuf(struct ak4524_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg) +{ + unsigned bufs; + + db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0; + if (!db->rawbuf) { + db->ready = db->mapped = 0; + db->rawbuf = kmalloc(PAGE_SIZE << DMABUF_DEFAULTORDER, GFP_KERNEL|GFP_DMA); + if (!db->rawbuf) + return -ENOMEM; + db->buforder = DMABUF_DEFAULTORDER; + db->dmaaddr = virt_to_phys(db->rawbuf); + } + DBG(printk("prog_dmabuf: rawbuf=0x%p, size=%d\n", db->rawbuf, (int)(PAGE_SIZE << DMABUF_DEFAULTORDER));) + DBG(printk("fmt = 0x%x, rate = 0x%x\n", fmt, rate);) + bufs = PAGE_SIZE << db->buforder; + + db->fragshift = DEFAULT_FRAGSHIFT; + db->numfrag = bufs >> db->fragshift; + db->fragsize = 1 << db->fragshift; + db->dmasize = db->numfrag << db->fragshift; + DBG(printk("fragshift=%d numfrag=%d fragsize=%d dmasize=%d\n", db->fragshift, db->numfrag, db->fragsize, db->dmasize);) + memset(db->rawbuf, (fmt & AFMT_S16_LE) ? 0 : 0x80, db->dmasize); + DBG(printk("prog_dmabuf: padding 0x%x\n", (fmt & AFMT_S16_LE)? 0:0x80);) + db->enabled = 1; + db->ready = 1; + return 0; +} + +static inline int prog_dmabuf_adc(struct ak4524_state *s) +{ + stop_adc(s); + return prog_dmabuf(s, &s->dma_adc, s->rate, s->rfmt, 0); +} + +static inline int prog_dmabuf_dac(struct ak4524_state *s) +{ + stop_dac(s); + return prog_dmabuf(s, &s->dma_dac, s->rate, s->pfmt, 0); +} + +static inline unsigned get_hwptr(struct ak4524_state *s, struct dmabuf *db, unsigned reg) +{ + unsigned hwptr, next_hwptr; + + hwptr = db->hwptr; + next_hwptr = (hwptr + db->fragsize) % db->dmasize; + db->hwptr = next_hwptr; + return db->fragsize; +} + +static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c) +{ + if (bptr + len > bsize) { + unsigned x = bsize - bptr; + memset(((char *)buf) + bptr, c, x); + bptr = 0; + len -= x; + } + memset(((char *)buf) + bptr, c, len); +} + +/* call with spinlock held! */ +static void ak4524_update_ptr(struct ak4524_state *s) +{ + int diff; + unsigned next_hwptr; + + /* update ADC pointer */ + if (s->ctrl & CTRL_ADC_EN) { + diff = get_hwptr(s, &s->dma_adc, 0); + s->dma_adc.total_bytes += diff; + s->dma_adc.count += diff; + if (s->dma_adc.count >= (signed)s->dma_adc.fragsize) { + /* address registers */ + outl(ASNDSIORXB, DMA_RSA); + next_hwptr = (s->dma_adc.hwptr + s->dma_adc.fragsize) % s->dma_adc.dmasize; + outl(s->dma_adc.dmaaddr + next_hwptr, DMA_RDA); + outl(s->dma_adc.fragsize, DMA_RBCUT); + DBG(printk("DMA_RDA = 0x%x\n", s->dma_adc.dmaaddr + next_hwptr);) + wake_up(&s->dma_adc.wait); + } + if (!s->dma_adc.mapped) { + if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) { + s->ctrl &= ~CTRL_ADC_EN; + s->dma_adc.error++; + } + } + } + /* update DAC1 pointer */ + if (s->ctrl & CTRL_DAC_EN) { + diff = get_hwptr(s, &s->dma_dac, 0); + s->dma_dac.total_bytes += diff; + if (s->dma_dac.mapped) { + s->dma_dac.count += diff; + if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) + wake_up(&s->dma_dac.wait); + } else { + s->dma_dac.count -= diff; + if (s->dma_dac.count <= 0) { + s->ctrl &= ~CTRL_DAC_EN; + s->dma_dac.error++; + DBG(printk("\nunderrun error %d\n", s->dma_dac.error);) + } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) { + clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr, + s->dma_dac.fragsize, (s->pfmt & AFMT_S16_LE) ? 0 : 0x80); + s->dma_dac.endcleared = 1; + outl(0, DMA_RBCUT); + DBG(printk("\nstop reload\n\n");) + } + if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize) { + /* address registers */ + next_hwptr = (s->dma_dac.hwptr + s->dma_dac.fragsize) % s->dma_dac.dmasize; + outl(s->dma_dac.dmaaddr + next_hwptr, DMA_RSA); + outl(ASNDSIOTXB_L, DMA_RDA); + outl(s->dma_dac.fragsize, DMA_RBCUT); + DBG(printk("DMA_RSA = 0x%x\n", s->dma_dac.dmaaddr + next_hwptr);) + wake_up(&s->dma_dac.wait); + } + } + } +} + +static irqreturn_t ak4524_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct ak4524_state *s = (struct ak4524_state *)dev_id; + unsigned long reg; + + if ((inl(DMAISTS) & DMAISTS_DISTS) == 0) { /* DMA ? */ + printk("ak4524_interrupt: not DMA\n"); + return IRQ_NONE; + } + + spin_lock(&s->lock); + + reg = inl(DMAEDET); + reg |= DMAEDET_DEDET; + outl(reg, DMAEDET); /* clear status */ + + /* clear audio interrupts first */ + + ak4524_update_ptr(s); + + spin_unlock(&s->lock); + return IRQ_HANDLED; +} + +/* --------------------------------------------------------------------- */ + +static const char invalid_magic[] = KERN_CRIT "ak4524: invalid magic value\n"; + +#define VALIDATE_STATE(s) \ +({ \ + if (!(s) || (s)->magic != AK4524_MAGIC) { \ + printk(invalid_magic); \ + return -ENXIO; \ + } \ +}) + +/* --------------------------------------------------------------------- */ + +static const struct { + unsigned volidx:4; + unsigned left:4; + unsigned right:4; + unsigned stereo:1; + unsigned recmask:13; + unsigned avail:1; +} mixtable[SOUND_MIXER_NRDEVICES] = { + [SOUND_MIXER_VOLUME] = { 0, 0x0, 0x1, 1, 0x0000, 1 }, /* master */ +// [SOUND_MIXER_PCM] = { 1, 0x2, 0x3, 1, 0x0400, 1 }, /* voice */ +// [SOUND_MIXER_SYNTH] = { 2, 0x4, 0x5, 1, 0x0060, 1 }, /* FM */ +// [SOUND_MIXER_CD] = { 3, 0x6, 0x7, 1, 0x0006, 1 }, /* CD */ +// [SOUND_MIXER_LINE] = { 4, 0x8, 0x9, 1, 0x0018, 1 }, /* Line */ +// [SOUND_MIXER_LINE1] = { 5, 0xa, 0xb, 1, 0x1800, 1 }, /* AUX */ +// [SOUND_MIXER_LINE2] = { 6, 0xc, 0x0, 0, 0x0100, 1 }, /* Mono1 */ +// [SOUND_MIXER_LINE3] = { 7, 0xd, 0x0, 0, 0x0200, 1 }, /* Mono2 */ + [SOUND_MIXER_MIC] = { 8, 0xe, 0x0, 1, 0x0001, 1 }, /* Mic */ +// [SOUND_MIXER_OGAIN] = { 9, 0xf, 0x0, 0, 0x0000, 1 } /* mono out */ +}; + +static void set_recsrc(struct ak4524_state *s, unsigned int val) +{ + unsigned int i, j; + + DBG(printk("set_recsrc:\n");) + for (j = i = 0; i < SOUND_MIXER_NRDEVICES; i++) { + if (!(val & (1 << i))) + continue; + if (!mixtable[i].recmask) { + val &= ~(1 << i); + continue; + } + j |= mixtable[i].recmask; + } + s->mix.recsrc = val; + /* + * need to set codec? + */ +} + +static int mixer_ioctl(struct ak4524_state *s, unsigned int cmd, unsigned long arg) +{ + int i, val; + unsigned char l, r, rl, rr; + int __user *p = (int __user *)arg; + + VALIDATE_STATE(s); + if (cmd == SOUND_MIXER_INFO) { + mixer_info info; + DBG(printk("SOUND_MIXER_INFO:\n");) + /* enable/disable/query microphone impedance setting */ + strncpy(info.id, "AK4524", sizeof(info.id)); + strncpy(info.name, "Asahi Kasei AK4524", sizeof(info.name)); + info.modify_counter = s->mix.modcnt; + if (copy_to_user(p, &info, sizeof(info))) + return -EFAULT; + return 0; + } + if (cmd == SOUND_OLD_MIXER_INFO) { + _old_mixer_info info; + DBG(printk("SOUND_OLD_MIXER_INFO:\n");) + strncpy(info.id, "AK4524", sizeof(info.id)); + strncpy(info.name, "Asahi Kasei AK4524", sizeof(info.name)); + if (copy_to_user(p, &info, sizeof(info))) + return -EFAULT; + return 0; + } + if (cmd == OSS_GETVERSION) { + DBG(printk("OSS_GETVERSION:\n");) + return put_user(SOUND_VERSION, p); + } + if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int)) + return -EINVAL; + if (_SIOC_DIR(cmd) == _SIOC_READ) { + switch (_IOC_NR(cmd)) { + case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */ + return put_user(s->mix.recsrc, p); + + case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */ + val = SOUND_MASK_IMIX; + for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) + if (mixtable[i].avail) + val |= 1 << i; + return put_user(val, p); + + case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */ + for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++) + if (mixtable[i].recmask) + val |= 1 << i; + return put_user(val, p); + + case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */ + for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++) + if (mixtable[i].stereo) + val |= 1 << i; + return put_user(val, p); + + case SOUND_MIXER_CAPS: + DBG(printk("SOUND_MIXER_CAPS:\n");) + return put_user(0, p); + + case SOUND_MIXER_IMIX: + return put_user(s->mix.imix, p); + + default: + i = _IOC_NR(cmd); + if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail) + return -EINVAL; + return put_user(s->mix.vol[mixtable[i].volidx], p); + } + } + if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE)) + return -EINVAL; + s->mix.modcnt++; + switch (_IOC_NR(cmd)) { + + case SOUND_MIXER_IMIX: + if (get_user(s->mix.imix, p)) + return -EFAULT; + set_recsrc(s, s->mix.recsrc); + return 0; + + case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */ + if (get_user(val, p)) + return -EFAULT; + set_recsrc(s, val); + return 0; + + default: + i = _IOC_NR(cmd); + if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail) + return -EINVAL; + if (get_user(val, p)) + return -EFAULT; + l = val & 0xff; + if (l > 100) + l = 100; + if (mixtable[i].stereo) { + r = (val >> 8) & 0xff; + if (r > 100) + r = 100; + rr = (MAX_ATT * r)/100; + switch (_IOC_NR(cmd)) { + case SOUND_MIXER_VOLUME: + /* OATT */ + s->oatt = rr; + wrcodec(SUBADDR7, (unsigned short)rr); + break; + case SOUND_MIXER_MIC: + /* IATT */ + s->iatt = rr; + wrcodec(SUBADDR5, (unsigned short)rr); + break; + default: + DBG(printk("unknown volume setting.\n");) + break; + } + rl = (MAX_ATT * l)/100; + } else { + rl = (MAX_ATT * l)/100; + r = l; + } + switch (_IOC_NR(cmd)) { + case SOUND_MIXER_VOLUME: + /* OATT */ + s->oatt = rl; + wrcodec(SUBADDR6, (unsigned short)rl); /* OATT */ + break; + case SOUND_MIXER_MIC: + /* IATT */ + s->iatt = rl; + wrcodec(SUBADDR4, (unsigned short)rl); /* IATT */ + break; + default: + DBG(printk("unknown volume setting.\n");) + break; + } +#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS + s->mix.vol[mixtable[i].volidx] = ((unsigned int)r << 8) | l; +#else + s->mix.vol[mixtable[i].volidx] = val; +#endif + return put_user(s->mix.vol[mixtable[i].volidx], p); + } +} + +/* --------------------------------------------------------------------- */ + +static int ak4524_open_mixdev(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + struct list_head *list; + struct ak4524_state *s; + + for (list = devs.next; ; list = list->next) { + if (list == &devs) + return -ENODEV; + s = list_entry(list, struct ak4524_state, devs); + if (s->dev_mixer == minor) + break; + } + VALIDATE_STATE(s); + file->private_data = s; + return nonseekable_open(inode, file); +} + +static int ak4524_release_mixdev(struct inode *inode, struct file *file) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + + VALIDATE_STATE(s); + return 0; +} + +static int ak4524_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +{ + return mixer_ioctl((struct ak4524_state *)file->private_data, cmd, arg); +} + +static /*const*/ struct file_operations ak4524_mixer_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .ioctl = ak4524_ioctl_mixdev, + .open = ak4524_open_mixdev, + .release = ak4524_release_mixdev, +}; + +/* --------------------------------------------------------------------- */ +static int drain_dac(struct ak4524_state *s, int nonblock) +{ + DECLARE_WAITQUEUE(wait, current); + unsigned long flags; + int count, tmo; + + DBG(printk("drain_dac:\n");) + if (s->dma_dac.mapped || !s->dma_dac.ready) + return 0; + add_wait_queue(&s->dma_dac.wait, &wait); + for (;;) { + __set_current_state(TASK_INTERRUPTIBLE); + spin_lock_irqsave(&s->lock, flags); + count = s->dma_dac.count; + spin_unlock_irqrestore(&s->lock, flags); + if (count <= 0) + break; + if (signal_pending(current)) + break; + if (nonblock) { + remove_wait_queue(&s->dma_dac.wait, &wait); + set_current_state(TASK_RUNNING); + return -EBUSY; + } + tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 + / s->rate; + DBG(printk("count=%d,tmo=%d\n", count, tmo);) +#if 0 + tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT]; +#else + tmo >>= 1; +#endif + if (!schedule_timeout(tmo + 1)) + DBG(printk(KERN_DEBUG "ak4524: dma timed out??\n");) + } + remove_wait_queue(&s->dma_dac.wait, &wait); + set_current_state(TASK_RUNNING); + if (signal_pending(current)) + return -ERESTARTSYS; + return 0; +} + +/* --------------------------------------------------------------------- */ +#define SWAP16(x) ((((x) & 0xff) << 8) | ((x) & 0xff00) >> 8) +void inline swap_sound(unsigned short *p, int cnt) +{ + int n = cnt / sizeof(unsigned short); + unsigned short val; + + if (! swap_data) return; + + for (;n > 0; n--) { + val = *p; + *p = SWAP16(val); + p++; + } +} + +static ssize_t ak4524_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + DECLARE_WAITQUEUE(wait, current); + ssize_t ret = 0; + unsigned long flags; + unsigned swptr; + int cnt; + + DBG(printk("ak4524_read:\n");) + VALIDATE_STATE(s); + if (s->dma_adc.mapped) + return -ENXIO; + if (!access_ok(VERIFY_WRITE, buffer, count)) + return -EFAULT; + down(&s->sem); + if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) + goto out; + + add_wait_queue(&s->dma_adc.wait, &wait); + while (count > 0) { + spin_lock_irqsave(&s->lock, flags); + swptr = s->dma_adc.swptr; + cnt = s->dma_adc.dmasize-swptr; + if (s->dma_adc.count < cnt) + cnt = s->dma_adc.count; + if (cnt <= 0) + __set_current_state(TASK_INTERRUPTIBLE); + spin_unlock_irqrestore(&s->lock, flags); + if (cnt > count) + cnt = count; + DBG(printk("cnt=%d\n", cnt);) + if (cnt <= 0) { + DBG(printk("s->dma_adc.enabled=%d\n", s->dma_adc.enabled);) + if (s->dma_adc.enabled) + start_adc(s); + if (file->f_flags & O_NONBLOCK) { + if (!ret) + ret = -EAGAIN; + goto out; + } + up(&s->sem); + schedule(); + if (signal_pending(current)) { + if (!ret) + ret = -ERESTARTSYS; + goto out; + } + down(&s->sem); + if (s->dma_adc.mapped) + { + ret = -ENXIO; + goto out; + } + continue; + } +#ifdef FLUSH_CACHE + local_flush_cache_copyback_all(); +#endif + /* swap big endian data to little endian data */ + if (s->rfmt == AFMT_S16_LE) + swap_sound(s->dma_adc.rawbuf + swptr, cnt); + + if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) { + if (!ret) + ret = -EFAULT; + goto out; + } + DBG(printk("copy_to_user(0x%p, 0x%p, %d)\n", buffer, s->dma_adc.rawbuf + swptr, cnt);) + + swptr = (swptr + cnt) % s->dma_adc.dmasize; + spin_lock_irqsave(&s->lock, flags); + s->dma_adc.swptr = swptr; + s->dma_adc.count -= cnt; + spin_unlock_irqrestore(&s->lock, flags); + count -= cnt; + buffer += cnt; + ret += cnt; + if (s->dma_adc.enabled) + start_adc(s); + } +out: + up(&s->sem); + remove_wait_queue(&s->dma_adc.wait, &wait); + set_current_state(TASK_RUNNING); + return ret; +} + +static ssize_t ak4524_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + DECLARE_WAITQUEUE(wait, current); + ssize_t ret = 0; + unsigned long flags; + unsigned swptr; + int cnt; + + DBG(printk("ak4524_write: count=%d\n", count);) + VALIDATE_STATE(s); + if (s->dma_dac.mapped) + return -ENXIO; + if (!access_ok(VERIFY_READ, buffer, count)) + return -EFAULT; + down(&s->sem); + if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s))) + goto out; + ret = 0; + add_wait_queue(&s->dma_dac.wait, &wait); + while (count > 0) { + spin_lock_irqsave(&s->lock, flags); + if (s->dma_dac.count < 0) { + s->dma_dac.count = 0; + s->dma_dac.swptr = s->dma_dac.hwptr; + } + swptr = s->dma_dac.swptr; + cnt = s->dma_dac.dmasize-swptr; + if (s->dma_dac.count + cnt > s->dma_dac.dmasize) + cnt = s->dma_dac.dmasize - s->dma_dac.count; + if (cnt <= 0) + __set_current_state(TASK_INTERRUPTIBLE); + spin_unlock_irqrestore(&s->lock, flags); + if (cnt > count) + cnt = count; + if (cnt <= 0) { + if (s->dma_dac.enabled) + start_dac(s); + if (file->f_flags & O_NONBLOCK) { + if (!ret) + ret = -EAGAIN; + goto out; + } + up(&s->sem); + schedule(); + if (signal_pending(current)) { + if (!ret) + ret = -ERESTARTSYS; + goto out; + } + down(&s->sem); + if (s->dma_dac.mapped) + { + ret = -ENXIO; + goto out; + } + continue; + } + if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) { + if (!ret) + ret = -EFAULT; + goto out; + } + /* swap little endian data to big endian data */ + if (s->pfmt == AFMT_S16_LE) + swap_sound(s->dma_dac.rawbuf + swptr, cnt); + +#ifdef FLUSH_CACHE + local_flush_cache_copyback_all(); +#endif + swptr = (swptr + cnt) % s->dma_dac.dmasize; + spin_lock_irqsave(&s->lock, flags); + s->dma_dac.swptr = swptr; + s->dma_dac.count += cnt; + s->dma_dac.endcleared = 0; + spin_unlock_irqrestore(&s->lock, flags); + count -= cnt; + buffer += cnt; + ret += cnt; + if (s->dma_dac.enabled) + start_dac(s); + } +out: + up(&s->sem); + remove_wait_queue(&s->dma_dac.wait, &wait); + set_current_state(TASK_RUNNING); + return ret; +} + +/* No kernel lock - we have our own spinlock */ +static unsigned int ak4524_poll(struct file *file, struct poll_table_struct *wait) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + unsigned long flags; + unsigned int mask = 0; + + DBG(printk("ak4524_poll:\n");) + VALIDATE_STATE(s); + if (file->f_mode & FMODE_WRITE) { + if (!s->dma_dac.ready && prog_dmabuf_dac(s)) + return 0; + poll_wait(file, &s->dma_dac.wait, wait); + } + if (file->f_mode & FMODE_READ) { + if (!s->dma_adc.ready && prog_dmabuf_adc(s)) + return 0; + poll_wait(file, &s->dma_adc.wait, wait); + } + spin_lock_irqsave(&s->lock, flags); + //ak4524_update_ptr(s); + if (file->f_mode & FMODE_READ) { + if (s->dma_adc.count >= (signed)s->dma_adc.fragsize) + mask |= POLLIN | POLLRDNORM; + } + if (file->f_mode & FMODE_WRITE) { + if (s->dma_dac.mapped) { + if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) + mask |= POLLOUT | POLLWRNORM; + } else { + if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize) + mask |= POLLOUT | POLLWRNORM; + } + } + spin_unlock_irqrestore(&s->lock, flags); + return mask; +} + +static int ak4524_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + struct dmabuf *db; + int ret = 0; + unsigned long size; + + DBG(printk("ak4524_mmap:\n");) + VALIDATE_STATE(s); + lock_kernel(); + down(&s->sem); + if (vma->vm_flags & VM_WRITE) { + if ((ret = prog_dmabuf_dac(s)) != 0) { + goto out; + } + db = &s->dma_dac; + } else if (vma->vm_flags & VM_READ) { + if ((ret = prog_dmabuf_adc(s)) != 0) { + goto out; + } + db = &s->dma_adc; + } else { + ret = -EINVAL; + goto out; + } + if (vma->vm_pgoff != 0) { + ret = -EINVAL; + goto out; + } + size = vma->vm_end - vma->vm_start; + if (size > (PAGE_SIZE << db->buforder)) { + ret = -EINVAL; + goto out; + } + if (remap_pfn_range(vma, vma->vm_start, + virt_to_phys(db->rawbuf) >> PAGE_SHIFT, + size, vma->vm_page_prot)) { + ret = -EAGAIN; + goto out; + } + db->mapped = 1; +out: + up(&s->sem); + unlock_kernel(); + return ret; +} + +static int ak4524_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + unsigned long flags; + audio_buf_info abinfo; + count_info cinfo; + int count; + int val, mapped, ret; + void __user *argp = (void __user *)arg; + int __user *p = argp; + + DBG(printk("ak4524_ioctl:\n");) + VALIDATE_STATE(s); + mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) || + ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); + switch (cmd) { + case OSS_GETVERSION: + DBG(printk("ak4524_ioctl OSS_GETVErSION:\n");) + return put_user(SOUND_VERSION, p); + + case SNDCTL_DSP_SYNC: + DBG(printk("ak4524_ioctl SNDCTL_DSP_SYNC:\n");) + if (file->f_mode & FMODE_WRITE) + return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/); + return 0; + + case SNDCTL_DSP_SETDUPLEX: + DBG(printk("ak4524_ioctl SNDCTL_DSP_SESTDUPLEX:\n");) + return 0; + + case SNDCTL_DSP_GETCAPS: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETCAPS:\n");) + return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p); + + case SNDCTL_DSP_RESET: + DBG(printk("ak4524_ioctl SNDCTL_DSP_RESET:\n");) + if (file->f_mode & FMODE_WRITE) { + stop_dac(s); + synchronize_irq(s->irq); + s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0; + } + if (file->f_mode & FMODE_READ) { + stop_adc(s); + synchronize_irq(s->irq); + s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0; + } + return 0; + + case SNDCTL_DSP_SPEED: + DBG(printk("ak4524_ioctl SNDCTL_DSP_SPEED:\n");) + if (get_user(val, p)) + return -EFAULT; + if (val >= 0) { + if (s->open_mode & (~file->f_mode) & (FMODE_READ|FMODE_WRITE)) + return -EINVAL; + switch (val) { + case 44100: + case 22050: + case 11025: + case 8820: + break; + default: + val = DEFAULT_RATE; + } + stop_adc(s); + stop_dac(s); + s->dma_adc.ready = s->dma_dac.ready = 0; + spin_lock_irqsave(&s->lock, flags); + if (s->rate != val) { + s->rate = val; + if (file->f_mode & FMODE_WRITE) + start_AK4524(s->pfmt, s->rate, 0, s->iatt, s->oatt); + if (file->f_mode & FMODE_READ) + start_AK4524(s->rfmt, s->rate, 1, s->iatt, s->oatt); + } + spin_unlock_irqrestore(&s->lock, flags); + } + return put_user(s->rate, p); + + case SNDCTL_DSP_STEREO: + DBG(printk("ak4524_ioctl SNDCTL_DSP_STEREO:\n");) + if (get_user(val, p)) + return -EFAULT; + if (file->f_mode & FMODE_READ) { + stop_adc(s); + s->dma_adc.ready = 0; + spin_lock_irqsave(&s->lock, flags); + if (val) + s->rchannels = 2; + else + s->rchannels = 1; + spin_unlock_irqrestore(&s->lock, flags); + } + if (file->f_mode & FMODE_WRITE) { + stop_dac(s); + s->dma_dac.ready = 0; + spin_lock_irqsave(&s->lock, flags); + if (val) + s->pchannels = 2; + else + s->pchannels = 1; + spin_unlock_irqrestore(&s->lock, flags); + } + return 0; + + case SNDCTL_DSP_CHANNELS: + DBG(printk("ak4524_ioctl SNDCTL_DSP_CHANNELS:\n");) + if (get_user(val, p)) + return -EFAULT; + if (val != 0) { + if (file->f_mode & FMODE_READ) { + stop_adc(s); + s->dma_adc.ready = 0; + spin_lock_irqsave(&s->lock, flags); + if (val >= 2) + s->rchannels = 2; + else + s->rchannels = 1; + spin_unlock_irqrestore(&s->lock, flags); + } + if (file->f_mode & FMODE_WRITE) { + stop_dac(s); + s->dma_dac.ready = 0; + spin_lock_irqsave(&s->lock, flags); + if (val >= 2) + s->pchannels = 2; + else + s->pchannels = 1; + spin_unlock_irqrestore(&s->lock, flags); + } + } + return put_user((file->f_mode & FMODE_READ) ? s->rchannels : s->pchannels, p); + + case SNDCTL_DSP_GETFMTS: /* Returns a mask */ + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETFMTS:\n");) + return put_user(AFMT_S16_LE|AFMT_S16_BE|AFMT_U8, p); + + case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/ + DBG(printk("ak4524_ioctl SNDCTL_DSP_SETFMT:\n");) + if (get_user(val, p)) + return -EFAULT; + if (val != AFMT_QUERY) { + if (file->f_mode & FMODE_READ) { + stop_adc(s); + s->dma_adc.ready = 0; + if (val == AFMT_S16_LE || val == AFMT_S16_BE) { + spin_lock_irqsave(&s->lock, flags); + s->rfmt = val; + spin_unlock_irqrestore(&s->lock, flags); + } else + return -EINVAL; + } + if (file->f_mode & FMODE_WRITE) { + stop_dac(s); + s->dma_dac.ready = 0; + if (val == AFMT_S16_LE || val == AFMT_S16_BE) { + spin_lock_irqsave(&s->lock, flags); + s->pfmt = val; + spin_unlock_irqrestore(&s->lock, flags); + } else + return -EINVAL; + } + } + return put_user((file->f_mode & FMODE_READ) ? s->rfmt: s->pfmt, p); + + case SNDCTL_DSP_POST: + DBG(printk("ak4524_ioctl SNDCTL_DSP_POST:\n");) + return 0; + + case SNDCTL_DSP_GETTRIGGER: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETTRIGGER:\n");) + val = 0; + if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN) + val |= PCM_ENABLE_INPUT; + if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC_EN) + val |= PCM_ENABLE_OUTPUT; + return put_user(val, p); + + case SNDCTL_DSP_SETTRIGGER: + DBG(printk("ak4524_ioctl SNDCTL_DSP_SETTRIGGER:\n");) + if (get_user(val, p)) + return -EFAULT; + if (file->f_mode & FMODE_READ) { + if (val & PCM_ENABLE_INPUT) { + if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) + return ret; + s->dma_adc.enabled = 1; + start_adc(s); + } else { + s->dma_adc.enabled = 0; + stop_adc(s); + } + } + if (file->f_mode & FMODE_WRITE) { + if (val & PCM_ENABLE_OUTPUT) { + if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s))) + return ret; + s->dma_dac.enabled = 1; + start_dac(s); + } else { + s->dma_dac.enabled = 0; + stop_dac(s); + } + } + return 0; + + case SNDCTL_DSP_GETOSPACE: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETOSPACE:\n");) + if (!(file->f_mode & FMODE_WRITE)) + return -EINVAL; + if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0) + return val; + spin_lock_irqsave(&s->lock, flags); + //ak4524_update_ptr(s); + abinfo.fragsize = s->dma_dac.fragsize; + count = s->dma_dac.count; + if (count < 0) + count = 0; + abinfo.bytes = s->dma_dac.dmasize - count; + abinfo.fragstotal = s->dma_dac.numfrag; + abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; + spin_unlock_irqrestore(&s->lock, flags); + DBG(printk(" abinfo.fragsize=%d\n", abinfo.fragsize);) + DBG(printk(" abinfo.bytes=%d\n", abinfo.bytes);) + DBG(printk(" abinfo.fragstotal=%d\n", abinfo.fragstotal);) + DBG(printk(" abinfo.fragments=%d\n", abinfo.fragments);) + return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; + + case SNDCTL_DSP_GETISPACE: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETISPACE:\n");) + if (!(file->f_mode & FMODE_READ)) + return -EINVAL; + if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0) + return val; + spin_lock_irqsave(&s->lock, flags); + //ak4524_update_ptr(s); + abinfo.fragsize = s->dma_adc.fragsize; + count = s->dma_adc.count; + if (count < 0) + count = 0; + abinfo.bytes = count; + abinfo.fragstotal = s->dma_adc.numfrag; + abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift; + spin_unlock_irqrestore(&s->lock, flags); + return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; + + case SNDCTL_DSP_NONBLOCK: + DBG(printk("ak4524_ioctl SNDCTL_DSP_NONBLOCK:\n");) + file->f_flags |= O_NONBLOCK; + return 0; + + case SNDCTL_DSP_GETODELAY: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETODELAY:\n");) + if (!(file->f_mode & FMODE_WRITE)) + return -EINVAL; + if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0) + return val; + spin_lock_irqsave(&s->lock, flags); + //ak4524_update_ptr(s); + count = s->dma_dac.count; + spin_unlock_irqrestore(&s->lock, flags); + if (count < 0) + count = 0; + DBG(printk(" GETODELAY count=%d:\n", count);) + return put_user(count, p); + + case SNDCTL_DSP_GETIPTR: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETIPTR:\n");) + if (!(file->f_mode & FMODE_READ)) + return -EINVAL; + if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0) + return val; + spin_lock_irqsave(&s->lock, flags); + //ak4524_update_ptr(s); + cinfo.bytes = s->dma_adc.total_bytes; + count = s->dma_adc.count; + if (count < 0) + count = 0; + cinfo.blocks = count >> s->dma_adc.fragshift; + cinfo.ptr = s->dma_adc.hwptr; + if (s->dma_adc.mapped) + s->dma_adc.count &= s->dma_adc.fragsize-1; + spin_unlock_irqrestore(&s->lock, flags); + if(copy_to_user(argp, &cinfo, sizeof(cinfo))) + return -EFAULT; + return 0; + + case SNDCTL_DSP_GETOPTR: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETOPTR:\n");) + if (!(file->f_mode & FMODE_WRITE)) + return -EINVAL; + if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0) + return val; + spin_lock_irqsave(&s->lock, flags); + //ak4524_update_ptr(s); + cinfo.bytes = s->dma_dac.total_bytes; + count = s->dma_dac.count; + if (count < 0) + count = 0; + cinfo.blocks = count >> s->dma_dac.fragshift; + cinfo.ptr = s->dma_dac.hwptr; + if (s->dma_dac.mapped) + s->dma_dac.count &= s->dma_dac.fragsize-1; + spin_unlock_irqrestore(&s->lock, flags); + if(copy_to_user(argp, &cinfo, sizeof(cinfo))) + return -EFAULT; + return 0; + + case SNDCTL_DSP_GETBLKSIZE: + DBG(printk("ak4524_ioctl SNDCTL_DSP_GETBLKSIZE:\n");) + if (file->f_mode & FMODE_WRITE) { + if ((val = prog_dmabuf_dac(s))) + return val; + return put_user(s->dma_dac.fragsize, p); + } + if ((val = prog_dmabuf_adc(s))) + return val; + return put_user(s->dma_adc.fragsize, p); + + case SNDCTL_DSP_SETFRAGMENT: + DBG(printk("ak4524_ioctl SNDCTL_DSP_SETFRAGMENT:\n");) + if (get_user(val, p)) + return -EFAULT; + if (file->f_mode & FMODE_READ) { + s->dma_adc.ossfragshift = val & 0xffff; + s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff; + if (s->dma_adc.ossfragshift < 4) + s->dma_adc.ossfragshift = 4; + if (s->dma_adc.ossfragshift > 15) + s->dma_adc.ossfragshift = 15; + if (s->dma_adc.ossmaxfrags < 4) + s->dma_adc.ossmaxfrags = 4; + } + if (file->f_mode & FMODE_WRITE) { + s->dma_dac.ossfragshift = val & 0xffff; + s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff; + if (s->dma_dac.ossfragshift < 4) + s->dma_dac.ossfragshift = 4; + if (s->dma_dac.ossfragshift > 15) + s->dma_dac.ossfragshift = 15; + if (s->dma_dac.ossmaxfrags < 4) + s->dma_dac.ossmaxfrags = 4; + } + return 0; + + case SNDCTL_DSP_SUBDIVIDE: + DBG(printk("ak4524_ioctl SNDCTL_DSP_SUBDIVIDE:\n");) + if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) || + (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision)) + return -EINVAL; + if (get_user(val, p)) + return -EFAULT; + if (val != 1 && val != 2 && val != 4) + return -EINVAL; + if (file->f_mode & FMODE_READ) + s->dma_adc.subdivision = val; + if (file->f_mode & FMODE_WRITE) + s->dma_dac.subdivision = val; + return 0; + + case SOUND_PCM_READ_RATE: + DBG(printk("ak4524_ioctl SNDCTL_PCM_READ_RATE:\n");) + return put_user(s->rate, p); + + case SOUND_PCM_READ_CHANNELS: + DBG(printk("ak4524_ioctl SNDCTL_PCM_READ_CHANNELS:\n");) + return put_user((file->f_mode & FMODE_READ) ? s->rchannels : s->pchannels, p); + + case SOUND_PCM_READ_BITS: + DBG(printk("ak4524_ioctl SNDCTL_PCM_READ_BITS:\n");) + return put_user((file->f_mode & FMODE_READ) ? 16 : 8, p); + + case SOUND_PCM_WRITE_FILTER: + case SNDCTL_DSP_SETSYNCRO: + case SOUND_PCM_READ_FILTER: + DBG(printk("ak4524_ioctl SNDCTL_PCM_READ_FILER:\n");) + return -EINVAL; + + } + return mixer_ioctl(s, cmd, arg); +} + +static int ak4524_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + DECLARE_WAITQUEUE(wait, current); + unsigned long flags; + struct list_head *list; + struct ak4524_state *s; + + DBG(printk("ak4524_open:\n");) + for (list = devs.next; ; list = list->next) { + if (list == &devs) + return -ENODEV; + s = list_entry(list, struct ak4524_state, devs); + if (!((s->dev_audio ^ minor) & ~0xf)) + break; + } + VALIDATE_STATE(s); + file->private_data = s; + /* wait for device to become free */ + down(&s->open_sem); + while (s->open_mode & file->f_mode) { + if (file->f_flags & O_NONBLOCK) { + up(&s->open_sem); + return -EBUSY; + } + add_wait_queue(&s->open_wait, &wait); + __set_current_state(TASK_INTERRUPTIBLE); + up(&s->open_sem); + schedule(); + remove_wait_queue(&s->open_wait, &wait); + set_current_state(TASK_RUNNING); + if (signal_pending(current)) + return -ERESTARTSYS; + down(&s->open_sem); + } + spin_lock_irqsave(&s->lock, flags); + if (!(s->open_mode & (FMODE_READ|FMODE_WRITE))) { + s->rate = DEFAULT_RATE; + } + if (file->f_mode & FMODE_READ) { + s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0; + s->dma_adc.enabled = 1; + if ((minor & 0xf) == SND_DEV_DSP16) + s->rfmt = AFMT_S16_LE; + else + s->rfmt = AFMT_U8; + DBG(printk("open: FMODE_READ\n");) + start_AK4524(s->rfmt, s->rate, 1, s->iatt, s->oatt); + } + if (file->f_mode & FMODE_WRITE) { + s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0; + s->dma_dac.enabled = 1; + if ((minor & 0xf) == SND_DEV_DSP16) + s->pfmt = AFMT_S16_LE; + else + s->pfmt = AFMT_U8; + DBG(printk("open: FMODE_WRITE\n");) + start_AK4524(s->pfmt, s->rate, 0, s->iatt, s->oatt); + } + spin_unlock_irqrestore(&s->lock, flags); + s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); + up(&s->open_sem); + init_MUTEX(&s->sem); + return nonseekable_open(inode, file); +} + +static int ak4524_release(struct inode *inode, struct file *file) +{ + struct ak4524_state *s = (struct ak4524_state *)file->private_data; + + DBG(printk("ak4524_release:\n");) + VALIDATE_STATE(s); + lock_kernel(); + if (file->f_mode & FMODE_WRITE) + drain_dac(s, file->f_flags & O_NONBLOCK); + down(&s->open_sem); + if (file->f_mode & FMODE_WRITE) { + stop_dac(s); + synchronize_irq(s->irq); + dealloc_dmabuf(s, &s->dma_dac); + } + if (file->f_mode & FMODE_READ) { + stop_adc(s); + dealloc_dmabuf(s, &s->dma_adc); + } + stop_AK4524(); + s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE)); + wake_up(&s->open_wait); + up(&s->open_sem); + unlock_kernel(); + return 0; +} + +static /*const*/ struct file_operations ak4524_audio_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .read = ak4524_read, + .write = ak4524_write, + .poll = ak4524_poll, + .ioctl = ak4524_ioctl, + .mmap = ak4524_mmap, + .open = ak4524_open, + .release = ak4524_release, +}; + +/* --------------------------------------------------------------------- */ + +/* maximum number of devices; only used for command line params */ +#define NR_DEVICE 5 + +static unsigned int devindex = 0; + +MODULE_AUTHOR("Takeo Takahashi "); +MODULE_DESCRIPTION("AK4524 Audio Driver"); +MODULE_LICENSE("GPL"); + + +/* --------------------------------------------------------------------- */ + +static struct initvol { + int mixch; + int vol; +} initvol[] __devinitdata = { + { SOUND_MIXER_WRITE_VOLUME, 0x0a0a }, +// { SOUND_MIXER_WRITE_PCM, 0x4040 }, +// { SOUND_MIXER_WRITE_SYNTH, 0x4040 }, +// { SOUND_MIXER_WRITE_CD, 0x4040 }, +// { SOUND_MIXER_WRITE_LINE, 0x4040 }, +// { SOUND_MIXER_WRITE_LINE1, 0x4040 }, +// { SOUND_MIXER_WRITE_LINE2, 0x4040 }, +// { SOUND_MIXER_WRITE_LINE3, 0x4040 }, + { SOUND_MIXER_WRITE_MIC, 0x7f7f }, +// { SOUND_MIXER_WRITE_OGAIN, 0x4040 } +}; + +static int __devinit ak4524_probe(void) +{ + struct ak4524_state *s; + mm_segment_t fs; + int i, val, ret; + + if (!(s = kmalloc(sizeof(struct ak4524_state), GFP_KERNEL))) { + printk(KERN_WARNING "ak4524: out of memory\n"); + return -ENOMEM; + } + memset(s, 0, sizeof(struct ak4524_state)); + init_waitqueue_head(&s->dma_adc.wait); + init_waitqueue_head(&s->dma_dac.wait); + init_waitqueue_head(&s->open_wait); + init_MUTEX(&s->open_sem); + spin_lock_init(&s->lock); + s->magic = AK4524_MAGIC; + s->dev = 0; + s->io = AUDXTICR; + s->irq = DMA_IRQ; + if ((ret=request_irq(s->irq, ak4524_interrupt, SA_INTERRUPT, "ak4524", s))) { + printk(KERN_ERR "ak4524: irq %u in use\n", s->irq); + goto err_irq; + } + + /* initialize codec registers */ + s->rate = DEFAULT_RATE; + s->rfmt = AFMT_S16_LE; + s->pfmt = AFMT_S16_LE; + s->rchannels = 2; + s->pchannels = 2; + s->oatt = 10; + s->iatt = 10; + printk(KERN_INFO "ak4524: found adapter at io %#lx irq %u dma %#x\n", s->io, s->irq, DMA_CR0); + printk(KERN_INFO "ak4524: swap_data %d\n", swap_data); + /* register devices */ + if ((s->dev_audio = register_sound_dsp(&ak4524_audio_fops, -1)) < 0) { + ret = s->dev_audio; + goto err_dev1; + } + if ((s->dev_mixer = register_sound_mixer(&ak4524_mixer_fops, -1)) < 0) { + ret = s->dev_mixer; + goto err_dev2; + } + + /* initialize the chips */ + init_port(); + init_audio(); + start_AK4524(s->pfmt, s->rate, 0, s->iatt, s->oatt); + + s->mix.imix = 1; + + fs = get_fs(); + set_fs(KERNEL_DS); + val = SOUND_MASK_MIC; + mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val); + for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) { + val = initvol[i].vol; + mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val); + } + set_fs(fs); + + /* put it into driver list */ + list_add_tail(&s->devs, &devs); + /* increment devindex */ + if (devindex < NR_DEVICE-1) + devindex++; + + /* reset AK4524 (PD# L by PLD) */ + outw(0x1, AUDPDCR); + wait_time(0x1000, 10); + return 0; + + err_dev2: + unregister_sound_dsp(s->dev_audio); + err_dev1: + printk(KERN_ERR "ak4524: cannot register misc device\n"); + free_irq(s->irq, s); + err_irq: + kfree(s); + return ret; +} + +static void __devexit ak4524_remove(void) +{ + struct list_head *list; + struct ak4524_state *s; + + DBG(printk("ak4524_remove:\n");) + + /* AK4524 Power Down */ + outw(0x0, AUDPDCR); + + for (list = devs.next; ; list = list->next) { + if (list == &devs) { + DBG(printk("list == &devs\n");) + return; + } + s = list_entry(list, struct ak4524_state, devs); + break; + } + + if (!s) + return; + list_del(&s->devs); + synchronize_irq(s->irq); + free_irq(s->irq, s); + unregister_sound_dsp(s->dev_audio); + unregister_sound_mixer(s->dev_mixer); + kfree(s); +} + +static int __init init_ak4524(void) +{ + printk(KERN_INFO "ak4524: Version v0.30 Time " __TIME__ " " __DATE__ "\n"); + return ak4524_probe(); +} + +static void __exit cleanup_ak4524(void) +{ + printk(KERN_INFO "ak4524: unloading\n"); + ak4524_remove(); +} + +module_init(init_ak4524); +module_exit(cleanup_ak4524); + +/* --------------------------------------------------------------------- */ + +#ifndef MODULE + +static int __init ak4524_setup(char *str) +{ + static unsigned __initdata nr_dev = 0; + + if (nr_dev >= NR_DEVICE) + return 0; + + nr_dev++; + return 1; +} + +__setup("ak4524=", ak4524_setup); + +#endif /* MODULE */