diff -ruN linux-2.4.26.org/arch/m32r/Makefile linux-2.4.26/arch/m32r/Makefile --- linux-2.4.26.org/arch/m32r/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/Makefile 2004-01-21 18:15:45.000000000 +0900 @@ -0,0 +1,133 @@ +# $Id: Makefile,v 1.18 2004/01/21 09:15:45 takata Exp $ + +# +# m32r/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. Remember to do have actions +# for "archclean" and "archdep" for cleaning up and making dependencies for +# this architecture +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 1994 Linus Torvalds +# Copyright (C) 1999 Kaz Kojima +# Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto +# + +# +# Select the object file format to substitute into the linker script. +# +ifdef CONFIG_CPU_LITTLE_ENDIAN +tool_prefix = m32rle-linux- +else +tool_prefix = m32r-linux- +endif + +CFLAGS := $(CFLAGS) -pipe -g -fno-schedule-insns + +CFLAGS_KERNEL += -mmodel=medium + +ifndef CONFIG_HAVE_M32R_MMU +CFLAGS := $(CFLAGS) -DNO_MM +AFLAGS := $(AFLAGS) -DNO_MM +endif + +ifdef CONFIG_ISA_M32R2 +# M32700, XNUX2 +CFLAGS := $(CFLAGS) -DNO_FPU -m32r2 +AFLAGS := $(AFLAGS) -DNO_FPU -m32r2 +else +# VDEC2 +CFLAGS := $(CFLAGS) -DNO_FPU -m32r -Wa,-bitinst +AFLAGS := $(AFLAGS) -DNO_FPU -m32r -Wa,-bitinst +endif + +# ifdef CONFIG_CROSSCOMPILE +CROSS_COMPILE = $(tool_prefix) +# endif + +LD = $(CROSS_COMPILE)ld $(LDFLAGS) +OBJDUMP = $(CROSS_COMPILE)objdump +OBJCOPY = $(CROSS_COMPILE)objcopy -O binary \ + -R .note -R .comment -R .stab -R .stabstr -S + +MODFLAGS += -mmodel=large -fno-builtin + +# +# Choosing incompatible machines durings configuration will result in +# error messages during linking. Select a default linkscript if +# none has been choosen above. +# +LINKSCRIPT = arch/m32r/vmlinux.lds +LINKFLAGS += -T $(word 1,$(LINKSCRIPT)) -e _stext + +ifdef LOADADDR +LINKFLAGS += -Ttext $(word 1,$(LOADADDR)) +endif + +HEAD := arch/m32r/kernel/head.o arch/m32r/kernel/init_task.o + +SUBDIRS := $(SUBDIRS) $(addprefix arch/m32r/, kernel mm lib boot) +CORE_FILES := arch/m32r/boot/boot.o arch/m32r/kernel/kernel.o \ + arch/m32r/mm/mm.o $(CORE_FILES) + +LIBGCC := $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) +LIBS := $(TOPDIR)/arch/m32r/lib/lib.a $(LIBS) $(LIBGCC) + +ifdef CONFIG_MATH_EMULATION +SUBDIRS += arch/m32r/math-emu +DRIVERS += arch/m32r/math-emu/math.o +endif + +SUBDIRS += arch/m32r/drivers +DRIVERS += arch/m32r/drivers/m32r_drivers.o + +MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot + +vmlinux.lis: vmlinux + $(OBJDUMP) -DS vmlinux >vmlinux.lis + +vmlinux.mot: vmlinux + $(OBJCOPY) -O srec vmlinux vmlinux.mot + +vmlinux: arch/m32r/vmlinux.lds + +arch/m32r/vmlinux.lds: arch/m32r/vmlinux.lds.S FORCE + $(CPP) $(AFLAGS) -traditional -C -P -I$(HPATH) \ + arch/m32r/vmlinux.lds.S >arch/m32r/vmlinux.lds + +FORCE: ; + +.PHONY: zImage bzImage compressed zdisk bzdisk install \ + clean archclean archmrproper archdep + +zImage: vmlinux + @$(MAKEBOOT) zImage + +bzImage: vmlinux + @$(MAKEBOOT) bzImage + +compressed: zImage + +zdisk: vmlinux + @$(MAKEBOOT) BOOTIMAGE=zImage zdisk + +bzdisk: vmlinux + @$(MAKEBOOT) BOOTIMAGE=bzImage zdisk + +install: vmlinux + @$(MAKEBOOT) BOOTIMAGE=bzImage install + +archclean: + @$(MAKEBOOT) clean + $(MAKE) -C arch/$(ARCH)/kernel clean +# $(MAKE) -C arch/$(ARCH)/tools clean + +archmrproper: + rm -f arch/m32r/vmlinux.lds + +archdep: + @$(MAKEBOOT) dep diff -ruN linux-2.4.26.org/arch/m32r/boot/Makefile linux-2.4.26/arch/m32r/boot/Makefile --- linux-2.4.26.org/arch/m32r/boot/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/Makefile 2003-12-17 10:10:26.000000000 +0900 @@ -0,0 +1,42 @@ +# +# arch/m32r/boot/Makefile +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# + +.S.o: + $(CC) $(AFLAGS) -traditional -c $< -o $*.o + +all: boot.o + +O_TARGET := boot.o + +obj-y := setup.o + +SYSTEM =$(TOPDIR)/vmlinux + +Image: $(SYSTEM) + $(OBJCOPY) $(SYSTEM) Image + +zImage: compressed/vmlinux + $(OBJCOPY) compressed/vmlinux zImage + +compressed/vmlinux: $(TOPDIR)/vmlinux + $(MAKE) CFLAGS="$(CFLAGS) $(CFLAGS_KERNEL)" -C compressed vmlinux + +install: Image + sh -x ./install.sh $(KERNELRELEASE) Image $(TOPDIR)/System.map "$(INSTALL_PATH)" + +zinstall: zImage + sh -x ./install.sh $(KERNELRELEASE) zImage $(TOPDIR)/System.map "$(INSTALL_PATH)" + +dep: + +clean: + rm -f zImage + @$(MAKE) -C compressed clean + +include $(TOPDIR)/Rules.make diff -ruN linux-2.4.26.org/arch/m32r/boot/compressed/Makefile linux-2.4.26/arch/m32r/boot/compressed/Makefile --- linux-2.4.26.org/arch/m32r/boot/compressed/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/compressed/Makefile 2004-01-21 03:20:52.000000000 +0900 @@ -0,0 +1,38 @@ +# +# linux/arch/m32r/boot/compressed/Makefile +# +# create a compressed vmlinux image from the original vmlinux +# + +.S.o: + $(CC) $(AFLAGS) -traditional -c $< -o $*.o + +HEAD = head.o +SYSTEM = $(TOPDIR)/vmlinux + +OBJECTS = $(HEAD) misc.o m32r_sio.o + +ZLDFLAGS = -e startup +ZLINKFLAGS = $(ZLDFLAGS) + +all: vmlinux + +vmlinux: piggy.o $(OBJECTS) vmlinux.lds + $(LD) $(ZLINKFLAGS) -o vmlinux $(OBJECTS) piggy.o -T vmlinux.lds + +piggy.o: $(SYSTEM) + $(OBJCOPY) $(SYSTEM) piggy + gzip -f -9 < piggy > piggy.gz + $(LD) -r -o $@ -b binary piggy.gz + +vmlinux.lds: vmlinux.lds.S FORCE + $(CPP) $(AFLAGS) -traditional -C -P -I$(HPATH) \ + vmlinux.lds.S > vmlinux.lds + +FORCE: ; + +clean: + rm -f vmlinux vmlinux.lds piggy piggy.o piggy.gz $(OBJECTS) + +include $(TOPDIR)/Rules.make + diff -ruN linux-2.4.26.org/arch/m32r/boot/compressed/boot.h linux-2.4.26/arch/m32r/boot/compressed/boot.h --- linux-2.4.26.org/arch/m32r/boot/compressed/boot.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/compressed/boot.h 2003-03-31 11:31:16.000000000 +0900 @@ -0,0 +1,59 @@ +/* + * 1. load vmlinuz + * + * CONFIG_MEMORY_START +-----------------------+ + * | vmlinuz | + * +-----------------------+ + * 2. decompressed + * + * CONFIG_MEMORY_START +-----------------------+ + * | vmlinuz | + * +-----------------------+ + * | | + * BOOT_RELOC_ADDR +-----------------------+ + * | | + * KERNEL_DECOMPRESS_ADDR +-----------------------+ + * | vmlinux | + * +-----------------------+ + * + * 3. relocate copy & jump code + * + * CONFIG_MEMORY_START +-----------------------+ + * | vmlinuz | + * +-----------------------+ + * | | + * BOOT_RELOC_ADDR +-----------------------+ + * | boot(copy&jump) | + * KERNEL_DECOMPRESS_ADDR +-----------------------+ + * | vmlinux | + * +-----------------------+ + * + * 4. relocate decompressed kernel + * + * CONFIG_MEMORY_START +-----------------------+ + * | vmlinux | + * +-----------------------+ + * | | + * BOOT_RELOC_ADDR +-----------------------+ + * | boot(copy&jump) | + * KERNEL_DECOMPRESS_ADDR +-----------------------+ + * | | + * +-----------------------+ + * + */ +#ifdef __ASSEMBLY__ +#define __val(x) x +#else +#define __val(x) (x) +#endif + +#define DECOMPRESS_OFFSET_BASE __val(0x00900000) +#define BOOT_RELOC_SIZE __val(0x00001000) + +#define KERNEL_EXEC_ADDR __val(CONFIG_MEMORY_START) +#define KERNEL_DECOMPRESS_ADDR __val(CONFIG_MEMORY_START + \ + DECOMPRESS_OFFSET_BASE + BOOT_RELOC_SIZE) +#define KERNEL_ENTRY __val(CONFIG_MEMORY_START + 0x1000) + +#define BOOT_EXEC_ADDR __val(CONFIG_MEMORY_START) +#define BOOT_RELOC_ADDR __val(CONFIG_MEMORY_START + DECOMPRESS_OFFSET_BASE) diff -ruN linux-2.4.26.org/arch/m32r/boot/compressed/head.S linux-2.4.26/arch/m32r/boot/compressed/head.S --- linux-2.4.26.org/arch/m32r/boot/compressed/head.S 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/compressed/head.S 2003-06-13 22:19:10.000000000 +0900 @@ -0,0 +1,201 @@ +/* + * linux/arch/m32r/boot/compressed/head.S + * + * Copyright (c) 2001-2003 Hiroyuki Kondo, Hirokazu Takata, + * Hitoshi Yamamoto, Takeo Takahashi + */ + + .text +#include +#include +#include +#include +#include +#include "boot.h" + + .global startup +startup: + ldi r0, #0x0000 /* SPI, disable EI */ + mvtc r0, psw + +/* + * Clear BSS first so that there are no surprises... + */ +#ifdef CONFIG_ISA_DUAL_ISSUE + + LDIMM (r2, SYMBOL_NAME(__bss_start)) + LDIMM (r3, SYMBOL_NAME(_end)) + sub r3, r2 ; BSS size in bytes + ; R4 = BSS size in longwords (rounded down) + mv r4, r3 || ldi r1, #0 + srli r4, #4 || addi r2, #-4 + beqz r4, .Lendloop1 +.Lloop1: +#ifndef CONFIG_CHIP_M32310 + ; Touch memory for the no-write-allocating cache. + ld r0, @(4,r2) +#endif + st r1, @+r2 || addi r4, #-1 + st r1, @+r2 + st r1, @+r2 + st r1, @+r2 || cmpeq r1, r4 ; R4 = 0? + bnc .Lloop1 +.Lendloop1: + and3 r4, r3, #15 + addi r2, #4 + beqz r4, .Lendloop2 +.Lloop2: + stb r1, @r2 || addi r4, #-1 + addi r2, #1 + bnez r4, .Lloop2 +.Lendloop2: + +#else /* not CONFIG_ISA_DUAL_ISSUE */ + + LDIMM (r2, SYMBOL_NAME(__bss_start)) + LDIMM (r3, SYMBOL_NAME(_end)) + sub r3, r2 ; BSS size in bytes + mv r4, r3 + srli r4, #2 ; R4 = BSS size in longwords (rounded down) + ldi r1, #0 ; clear R1 for longwords store + addi r2, #-4 ; account for pre-inc store + beqz r4, .Lendloop1 ; any more to go? +.Lloop1: + st r1, @+r2 ; yep, zero out another longword + addi r4, #-1 ; decrement count + bnez r4, .Lloop1 ; go do some more +.Lendloop1: + and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear + addi r2, #4 ; account for pre-inc store + beqz r4, .Lendloop2 ; any more to go? +.Lloop2: + stb r1, @r2 ; yep, zero out another byte + addi r2, #1 ; bump address + addi r4, #-1 ; decrement count + bnez r4, .Lloop2 ; go do some more +.Lendloop2: + +#endif /* not CONFIG_ISA_DUAL_ISSUE */ + + seth r0, #shigh(stack_start) + ld sp, @(r0, low(stack_start)) /* set stack point */ + +/* + * decompress the kernel + */ + bl decompress_kernel + mv r12, r0 /* size of decompressed kernel */ + +/* + * relocate copy routine & jump routine + */ + LDIMM (r1, BOOT_RELOC_ADDR) + mv r5, r1 ; save reloc addr to jump + + LDIMM (r2, SYMBOL_NAME(startup_reloc)) + LDIMM (r3, SYMBOL_NAME(exit_reloc)) + sub r3, r2 ; relocated code size in bytes + mv r4, r3 + srli r4, #2 ; R4 = code size in longwords (rounded down) + addi r1, #-4 ; account for pre-inc store + beqz r4, 2f ; any more to go? +1: + ld r6, @r2+ ; code to be relocated + st r6, @+r1 ; relocate code + addi r4, #-1 ; decrement count + bnez r4, 1b ; go do some more +2: + and3 r4, r3, #3 ; get no. of remaining bytes + addi r1, #4 ; account for pre-inc store + beqz r4, 4f ; any more to go? +3: + ldb r6, @r2 ; code to be relocated + stb r6, @r1 ; relocate code + addi r1, #1 ; bump address + addi r2, #1 ; bump address + addi r4, #-1 ; decrement count + bnez r4, 3b ; go do some more +4: + jmp r5 ; jump to relocated code + +/* + * startup_reloc runs on BOOT_RELOC_ADDR. + * copy decompressed kernel to original location + */ + .text + __ALIGN +startup_reloc: + LDIMM (r1, CONFIG_MEMORY_START) + LDIMM (r2, KERNEL_DECOMPRESS_ADDR) + mv r4, r12 ; r12 holds size of decompressed kernel + srli r4, #2 ; R4 = code size in longwords (rounded down) + addi r1, #-4 ; account for pre-inc store + beqz r4, 2f ; any more to go? +1: + ld r6, @r2+ ; code to be relocated + st r6, @+r1 ; relocate code + addi r4, #-1 ; decrement count + bnez r4, 1b ; go do some more +2: + and3 r4, r12, #3 ; get no. of remaining bytes + addi r1, #4 ; account for pre-inc store + beqz r4, 4f ; any more to go? +3: + ldb r6, @r2 ; code to be relocated + stb r6, @r1 ; relocate code + addi r1, #1 ; bump address + addi r2, #1 ; bump address + addi r4, #-1 ; decrement count + bnez r4, 3b ; go do some more +4: + /* + * invalidate i-cache before jump to kernel + */ +#if defined(CONFIG_CHIP_XNUX) + ldi r0, #-2 + ldi r1, #0x0100 ; invalidate + sth r1, @r0 +#elif defined(CONFIG_CHIP_XNUX2) + ldi r0, #-2 + ldi r1, #0x0100 ; invalidate + sth r1, @r0 +#elif defined(CONFIG_CHIP_M32700) + ldi r0, #-1 ; MCCR(cache control register) + ldi r1, #0xc0 ; invalidate i-cache + stb r1, @r0 +#elif defined(CONFIG_CHIP_M32310) + ldi r0, #-1 + ldi r1, #0xc0 ; invalidate i-cache + stb r1, #r0 +#elif defined(CONFIG_CHIP_NUX) + ldi r0, #-1 + ldi r1, #0xc0 ; invalidate i-cache + stb r1, @r0 +#else +#error unknown chip configuration +#endif + LDIMM (r0, KERNEL_ENTRY) + jmp r0 /* jump to kernel */ + + __ALIGN +exit_reloc: + + .balign 4096 +.fake_empty_zero_page: + /* FIXME: correct table value */ + .word 0 + .ascii "HdrS" + .word 0x0202 + .word 0 + .word 0 + .word 0x1000 + .word 0 + .byte 0 + .byte 1 + .word 0x8000 + .long 0 + .long 0 + + .section .fake_eit_vector, "aw" + .long 0 + diff -ruN linux-2.4.26.org/arch/m32r/boot/compressed/m32r_sio.c linux-2.4.26/arch/m32r/boot/compressed/m32r_sio.c --- linux-2.4.26.org/arch/m32r/boot/compressed/m32r_sio.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/compressed/m32r_sio.c 2003-09-16 19:24:21.000000000 +0900 @@ -0,0 +1,45 @@ +/* + * arch/m32r/boot/compressed/m32r_sio.c + * + * 2003-02-12: Takeo Takahashi + * + */ + +#include +#include +#include + +void putc(char c); + +void puts(char *s) +{ + char c; + while ((c = *s++)) putc(c); +} + +#if defined(CONFIG_PLAT_M32700UT_Alpha) || defined(CONFIG_PLAT_M32700UT) + +#if defined(CONFIG_PLAT_M32700UT_Alpha) +#define BOOT_SIO0STS (volatile unsigned short *)(0x02c00000 + 0x20006) +#define BOOT_SIO0TXB (volatile unsigned short *)(0x02c00000 + 0x2000c) +#elif defined(CONFIG_PLAT_M32700UT) +#define BOOT_SIO0STS PLD_ESIO0STS +#define BOOT_SIO0TXB PLD_ESIO0TXB +#endif + +void putc(char c) +{ + + while ((*BOOT_SIO0STS & 0x3) != 0x3) ; + if (c == '\n') { + *BOOT_SIO0TXB = '\r'; + while ((*BOOT_SIO0STS & 0x3) != 0x3) ; + } + *BOOT_SIO0TXB = c; +} +#else +void putc(char c) +{ + /* do nothing */ +} +#endif diff -ruN linux-2.4.26.org/arch/m32r/boot/compressed/misc.c linux-2.4.26/arch/m32r/boot/compressed/misc.c --- linux-2.4.26.org/arch/m32r/boot/compressed/misc.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/compressed/misc.c 2003-03-31 11:31:16.000000000 +0900 @@ -0,0 +1,224 @@ +/* + * arch/m32r/boot/compressed/misc.c + * + * This is a collection of several routines from gzip-1.0.3 + * adapted for Linux. + * + * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 + * + * Adapted for SH by Stuart Menefy, Aug 1999 + * + * Modified to use standard LinuxSH BIOS by Greg Banks 7Jul2000 + * + * 2003-02-12: Support M32R by Takeo Takahashi + * This is based on arch/sh/boot/compressed/misc.c. + */ + +#include +#include +#include "boot.h" + +/* + * gzip declarations + */ + +#define OF(args) args +#define STATIC static + +#undef memset +#undef memcpy +#define memzero(s, n) memset ((s), 0, (n)) + +typedef unsigned char uch; +typedef unsigned short ush; +typedef unsigned long ulg; + +#define WSIZE 0x8000 /* Window size must be at least 32k, */ + /* and a power of two */ + +static uch *inbuf; /* input buffer */ +static uch window[WSIZE]; /* Sliding window buffer */ + +static unsigned insize; /* valid bytes in inbuf */ +static unsigned inptr; /* index of next byte to be processed in inbuf */ +static unsigned outcnt; /* bytes in output buffer */ + +/* gzip flag byte */ +#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ +#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ +#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ +#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ +#define COMMENT 0x10 /* bit 4 set: file comment present */ +#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ +#define RESERVED 0xC0 /* bit 6,7: reserved */ + +#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf()) + +/* Diagnostic functions */ +#ifdef DEBUG +# define Assert(cond,msg) {if(!(cond)) error(msg);} +# define Trace(x) fprintf x +# define Tracev(x) {if (verbose) fprintf x ;} +# define Tracevv(x) {if (verbose>1) fprintf x ;} +# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} +# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} +#else +# define Assert(cond,msg) +# define Trace(x) +# define Tracev(x) +# define Tracevv(x) +# define Tracec(c,x) +# define Tracecv(c,x) +#endif + +static int fill_inbuf(void); +static void flush_window(void); +static void error(char *m); +static void gzip_mark(void **); +static void gzip_release(void **); + +extern char input_data[]; +extern int input_len; + +static long bytes_out; +static uch *output_data; +static unsigned long output_ptr; + + +static void *malloc(int size); +static void free(void *where); +static void error(char *m); +static void gzip_mark(void **); +static void gzip_release(void **); + +extern void puts(const char *); + +extern int _text; /* Defined in vmlinux.lds.S */ +extern int _end; +static unsigned long free_mem_ptr; +static unsigned long free_mem_end_ptr; + +#define HEAP_SIZE 0x10000 + +#include "../../../../lib/inflate.c" + +static void *malloc(int size) +{ + void *p; + + if (size <0) error("Malloc error\n"); + if (free_mem_ptr == 0) error("Memory error\n"); + + free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */ + + p = (void *)free_mem_ptr; + free_mem_ptr += size; + + if (free_mem_ptr >= free_mem_end_ptr) + error("\nOut of memory\n"); + + return p; +} + +static void free(void *where) +{ /* Don't care */ +} + +static void gzip_mark(void **ptr) +{ + *ptr = (void *) free_mem_ptr; +} + +static void gzip_release(void **ptr) +{ + free_mem_ptr = (long) *ptr; +} + +void* memset(void* s, int c, size_t n) +{ + int i; + char *ss = (char*)s; + + for (i=0;i> 8); + } + crc = c; + bytes_out += (ulg)outcnt; + output_ptr += (ulg)outcnt; + outcnt = 0; +} + +static void error(char *x) +{ + puts("\n\n"); + puts(x); + puts("\n\n -- System halted"); + + while(1); /* Halt */ +} + +#define STACK_SIZE (4096) +long user_stack [STACK_SIZE]; +long* stack_start = &user_stack[STACK_SIZE]; + +/* return decompressed size */ +long decompress_kernel(void) +{ + insize = 0; + inptr = 0; + bytes_out = 0; + outcnt = 0; + output_data = 0; + output_ptr = (unsigned long)KERNEL_DECOMPRESS_ADDR; + free_mem_ptr = (unsigned long)&_end; + free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; + + makecrc(); + puts("Uncompressing Linux... "); + gunzip(); + puts("Ok, booting the kernel.\n"); + return bytes_out; +} diff -ruN linux-2.4.26.org/arch/m32r/boot/compressed/vmlinux.lds.S linux-2.4.26/arch/m32r/boot/compressed/vmlinux.lds.S --- linux-2.4.26.org/arch/m32r/boot/compressed/vmlinux.lds.S 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/compressed/vmlinux.lds.S 2003-12-17 10:10:26.000000000 +0900 @@ -0,0 +1,107 @@ +#include +#include +#include + +OUTPUT_ARCH(m32r) +ENTRY(startup) +SECTIONS +{ + . = CONFIG_MEMORY_START + 0x00000000; + .fake_eit_vector : { *(.fake_eit_vector) } + + /* boot runs in physical address space */ + . = ALIGN(4096); + _text = .; + .text : + { + *(.text) + *(.fixup) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } = 0 + .text.lock : { *(.text.lock) } /* out-of-line lock text */ + .rodata : { *(.rodata) } + .kstrtab : { *(.kstrtab) } + _etext = .; /* End of text section */ + + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(32) + (. & (32 - 1)); + .data : + { + input_len = .; + LONG(input_data_end - input_data) + input_data = .; + piggy.o(.data) + input_data_end = .; + misc.o(.data) + m32r_sio.o(.data) + } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { *(.sdata) *(.sdata.*) } + _edata = .; + + . = ALIGN(32 / 8); + __bss_start = .; /* BSS */ + .sbss : { *(.sbss) *(.scommon) } + .bss : + { + *(.bss) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + } + . = ALIGN(32 / 8); + _end = . ; + + /* When something in the kernel is NOT compiled as a module, the + * module cleanup code and data are put into these segments. Both + * can then be thrown away, as cleanup code is never called unless + * it's a module. + */ + /DISCARD/ : { + *(.text.exit) + *(.data.exit) + *(.exitcall.exit) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* These must appear regardless of . */ +} diff -ruN linux-2.4.26.org/arch/m32r/boot/setup.S linux-2.4.26/arch/m32r/boot/setup.S --- linux-2.4.26.org/arch/m32r/boot/setup.S 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/boot/setup.S 2004-04-06 16:24:59.000000000 +0900 @@ -0,0 +1,210 @@ +/* + * linux/arch/m32r/boot/setup.S -- A setup code. + * + * Copyright (C) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata, + * and Hitoshi Yamamoto + * + */ +/* $Id: setup.S,v 1.25 2004/04/06 07:24:59 fujiwara Exp $ */ + +#include +#include +#include +#include +#include /* LDIMM() */ +#include /* MMU_REG_BASE */ + +#include +#include + +/* + * References to members of the boot_cpu_data structure. + */ + +#define CPU_PARAMS SYMBOL_NAME(boot_cpu_data) + +#define M32R_MCCR 0xfffffffc +#define M32R_BSCR0 0xffffffd2 + +;BSEL +#define BSEL0CR0 0x00ef5000 +#define BSEL0CR1 0x00ef5004 +#define BSEL1CR0 0x00ef5100 +#define BSEL1CR1 0x00ef5104 +#define BSEL0CR0_VAL 0x00000000 +#define BSEL0CR1_VAL 0x01200100 +#define BSEL1CR0_VAL 0x01018000 +#define BSEL1CR1_VAL 0x00200001 + +;SDRAMC +#define SDRAMC_SDRF0 0x00ef6000 +#define SDRAMC_SDRF1 0x00ef6004 +#define SDRAMC_SDIR0 0x00ef6008 +#define SDRAMC_SDIR1 0x00ef600c +#define SDRAMC_SD0ADR 0x00ef6020 +#define SDRAMC_SD0ER 0x00ef6024 +#define SDRAMC_SD0TR 0x00ef6028 +#define SDRAMC_SD0MOD 0x00ef602c +#define SDRAMC_SD1ADR 0x00ef6040 +#define SDRAMC_SD1ER 0x00ef6044 +#define SDRAMC_SD1TR 0x00ef6048 +#define SDRAMC_SD1MOD 0x00ef604c +#define SDRAM0 0x18000000 +#define SDRAM1 0x1c000000 + +/*------------------------------------------------------------------------ + * start up + */ + +/*------------------------------------------------------------------------ + * Kernel entry + */ + .section .boot,"ax" +ENTRY(boot) + +/* Set cache mode */ +#if defined(CONFIG_CHIP_XNUX2) + ldi r0, #-2 ;LDIMM (r0, M32R_MCCR) + ldi r1, #0x0101 ; cache on (with invalidation) +; ldi r1, #0x00 ; cache off + sth r1, @r0 +#elif defined(CONFIG_CHIP_VDEC2) + ; cache condition is controlled by loader + ; r13 = pointer to kernel parameter passed from loader + beqz r13, param_skip + ldi r2, #4096 ; size + seth r1, #high(empty_zero_page) + or3 r1, r1, #low(empty_zero_page) + seth r3, #high(__PAGE_OFFSET) + or3 r3, r3, #low(__PAGE_OFFSET) + not r3, r3 + and r1, r3 + addi r1, #-4 +param_loop: + ld r3, @r13+ + st r3, @+r1 + addi r2, #-4 + bnez r2, param_loop + bra param_end +param_skip: + ldi r0, #-1 ;LDIMM (r0, M32R_MCCR) + ldi r1, #0x63 ; cache on +; ldi r1, #0x00 ; cache off + stb r1, @r0 +param_end: + +#elif defined(CONFIG_CHIP_M32700) && (defined(CONFIG_PLAT_M32700UT) \ + || defined(CONFIG_PLAT_M32700UT_Alpha) || defined(CONFIG_PLAT_USRV)) + ; cache condition is controlled by loader + ; r13 = pointer to kernel parameter passed from loader + ldi r0, #-4 + ldi r1, #0x63 ; cache Ion/Don + st r1, @r0 +#if defined(CONFIG_SMP) && !defined(CONFIG_PLAT_USRV) + seth r5, #high(M32R_CPUID_PORTL) + or3 r5, r5, #low(M32R_CPUID_PORTL) + ld r5, @r5 + bnez r5, param_end + ;; boot AP + ld24 r5, #0xeff2f8 ; IPICR7 + ldi r6, #0x2 ; IPI to CPU1 + st r6, @r5 +#endif + beqz r13, param_end + ldi r2, #4096 ; size + seth r1, #high(empty_zero_page) + or3 r1, r1, #low(empty_zero_page) + seth r3, #high(__PAGE_OFFSET) + or3 r3, r3, #low(__PAGE_OFFSET) + not r3, r3 + and r1, r3 + addi r1, #-4 +param_loop: + ld r3, @r13+ + st r3, @+r1 + addi r2, #-4 + bnez r2, param_loop +param_end: +#elif defined(CONFIG_CHIP_M32700) + ldi r0, #-4 ;LDIMM (r0, M32R_MCCR) + ldi r1, #0x63 ; cache Ion/Don (with invalidation) +; ldi r1, #0x00 ; cache off + st r1, @r0 +#else +#error unknown chip configuration +#endif + +#ifdef CONFIG_SMP + ;; if not BSP (CPU#0) goto AP_loop + seth r5, #shigh(M32R_CPUID_PORTL) + ld r5, @(low(M32R_CPUID_PORTL), r5) + bnez r5, AP_loop +#endif + +/* + * Now, Jump to stext + * if with MMU, TLB on. + * if with no MMU, only jump. + */ +mmu_on: + LDIMM (r13,SYMBOL_NAME(stext)) +#ifdef CONFIG_HAVE_M32R_MMU + LDIMM (r2, SYMBOL_NAME(init_tlb)) + jl r2 + LDIMM (r2,SYMBOL_NAME(_RE)) ; set EVB(cr5) + mvtc r2, cr5 + seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher + or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower + ldi r1, #0x01 + st r1, @(MATM_offset,r0) ; Set MATM (T bit ON) + ld r0, @(MATM_offset,r0) ; Check +#endif + jmp r13 + nop + nop + + +#ifdef CONFIG_SMP + +/* + * AP wait loop + */ + +ENTRY(AP_loop) + ;; disable interrupt + clrpsw #0x0040 + ;; reset EVB + LDIMM (r4, SYMBOL_NAME(_AP_RE)) + seth r5, #high(__PAGE_OFFSET) + or3 r5, r5, #low(__PAGE_OFFSET) + not r5, r5 + and r4, r5 + mvtc r4, cr5 + ;; disable maskable interrupt + seth r4, #high(M32R_ICU_IMASK_PORTL) + or3 r4, r4, #low(M32R_ICU_IMASK_PORTL) + ldi r5, #0 + st r5, @r4 + ld r5, @r4 + ;; enable only IPI + setpsw #0x0040 + ;; LOOOOOOOOOOOOOOP!!! + .fillinsn +2: + nop + nop + bra 2b + nop + nop + +#ifdef CONFIG_CHIP_M32700_TS1 + .global dcache_dummy + .balign 16, 0 +dcache_dummy: + .byte 16 +#endif /* CONFIG_CHIP_M32700_TS1 */ + +#endif /* CONFIG_SMP */ + + .end + diff -ruN linux-2.4.26.org/arch/m32r/config.in linux-2.4.26/arch/m32r/config.in --- linux-2.4.26.org/arch/m32r/config.in 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/config.in 2004-03-22 10:55:18.000000000 +0900 @@ -0,0 +1,350 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/config-language.txt. +# +mainmenu_name "Linux/M32R Kernel Configuration" + +define_bool CONFIG_M32R y + +define_bool CONFIG_UID16 y +define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y + +mainmenu_option next_comment +comment 'Code maturity level options' +bool 'Prompt for development and/or incomplete code/drivers' CONFIG_EXPERIMENTAL +endmenu + +mainmenu_option next_comment +comment 'Loadable module support' +bool 'Enable loadable module support' CONFIG_MODULES +if [ "$CONFIG_MODULES" = "y" ]; then + bool ' Set version information on all module symbols' CONFIG_MODVERSIONS + bool ' Kernel module loader' CONFIG_KMOD +fi +endmenu + +mainmenu_option next_comment +comment 'Target processor type and platforms' +choice 'Target platform (eva. board)' \ + "Mappi CONFIG_PLAT_MAPPI \ + Mappi2 CONFIG_PLAT_MAPPI2 \ + M32700UT_Alpha CONFIG_PLAT_M32700UT_Alpha \ + M32700UT CONFIG_PLAT_M32700UT \ + uServer CONFIG_PLAT_USRV" M32700UT + +choice 'Processor type' \ + "M32700 CONFIG_CHIP_M32700 \ + XNUX2 CONFIG_CHIP_XNUX2 \ + VDEC2 CONFIG_CHIP_VDEC2" M32700 + +# ISA +if [ "$CONFIG_CHIP_XNUX2" = "y" -o \ + "$CONFIG_CHIP_M32700" = "y" ]; then + define_bool CONFIG_HAVE_M32R_MMU y + define_bool CONFIG_ISA_M32R2 y + define_bool CONFIG_ISA_DSP_LEVEL2 y +else + define_bool CONFIG_HAVE_M32R_MMU y + define_bool CONFIG_ISA_M32R2 n + define_bool CONFIG_ISA_M32R y + define_bool CONFIG_ISA_DSP_LEVEL2 n +fi + +# Dual issue +if [ "$CONFIG_CHIP_XNUX2" = "y" -o \ + "$CONFIG_CHIP_M32700" = "y" ]; then + bool 'Instruction dual issuing support' CONFIG_ISA_DUAL_ISSUE +fi + +# Platform-specific memory start and size definitions +if [ "$CONFIG_PLAT_MAPPI" = "y" ]; then + define_hex CONFIG_MEMORY_START 08000000 + define_hex CONFIG_MEMORY_SIZE 04000000 + define_int CONFIG_CPU_CLOCK 10000000 + define_int CONFIG_BUS_CLOCK 10000000 + define_int CONFIG_TIMER_DIVIDE 128 +fi +if [ "$CONFIG_PLAT_MAPPI2" = "y" ]; then + define_hex CONFIG_MEMORY_START 08000000 + define_hex CONFIG_MEMORY_SIZE 04000000 + define_int CONFIG_CPU_CLOCK 25000000 + define_int CONFIG_BUS_CLOCK 25000000 + define_int CONFIG_TIMER_DIVIDE 128 +fi +if [ "$CONFIG_PLAT_M32700UT_Alpha" = "y" ]; then + define_hex CONFIG_MEMORY_START 04000000 + define_hex CONFIG_MEMORY_SIZE 01000000 + define_int CONFIG_CPU_CLOCK 300000000 + define_int CONFIG_BUS_CLOCK 100000000 + define_int CONFIG_TIMER_DIVIDE 128 +fi +if [ "$CONFIG_PLAT_M32700UT" = "y" ]; then + define_hex CONFIG_MEMORY_START 08000000 + define_hex CONFIG_MEMORY_SIZE 01000000 + define_int CONFIG_CPU_CLOCK 300000000 + define_int CONFIG_BUS_CLOCK 100000000 + define_int CONFIG_TIMER_DIVIDE 128 +fi +if [ "$CONFIG_PLAT_USRV" = "y" ]; then + define_hex CONFIG_MEMORY_START 08000000 + define_hex CONFIG_MEMORY_SIZE 02000000 + define_int CONFIG_CPU_CLOCK 200000000 + define_int CONFIG_BUS_CLOCK 25000000 + define_int CONFIG_TIMER_DIVIDE 128 +fi + +bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN + +bool 'Use initrd' CONFIG_USE_INITRD y +if [ "$CONFIG_USE_INITRD" = "y" ]; then + if [ "$CONFIG_PLAT_MAPPI" = "y" ]; then + define_hex CONFIG_INITRD_START 082A0000 + define_hex CONFIG_INITRD_SIZE 0015F000 + fi + if [ "$CONFIG_PLAT_M32700UT_Alpha" = "y" ]; then + define_hex CONFIG_INITRD_START 04300000 + define_hex CONFIG_INITRD_SIZE 00400000 + fi + if [ "$CONFIG_PLAT_M32700UT" = "y" ]; then + define_hex CONFIG_INITRD_START 08300000 + define_hex CONFIG_INITRD_SIZE 00400000 + fi + if [ "$CONFIG_PLAT_USRV" = "y" ]; then + define_hex CONFIG_INITRD_START 08300000 + define_hex CONFIG_INITRD_SIZE 00400000 + fi + bool 'Initrd address user definition' CONFIG_INITRD_ADDR y + if [ "$CONFIG_INITRD_ADDR" = "y" ]; then + hex 'Initrd start physical address' CONFIG_INITRD_START 0 + hex 'Initrd size' CONFIG_INITRD_SIZE 0 + fi +fi + +#bool 'Math emulation' CONFIG_MATH_EMULATION + +if [ "$CONFIG_CHIP_XNUX2" = "y" -o \ + "$CONFIG_CHIP_M32700" = "y" ]; then + bool 'Symmetric multi-processing support' CONFIG_SMP +fi +if [ "$CONFIG_SMP" = "y" ]; then + int 'Maximum number of CPUs (2-32)' CONFIG_NR_CPUS 2 + if [ "$CONFIG_CHIP_M32700" = "y" ]; then + bool 'M32700 TS1 chip bug' CONFIG_CHIP_M32700_TS1 + fi +fi + +source arch/m32r/drivers/Config.in + +endmenu + + +mainmenu_option next_comment +comment 'General setup' + +bool 'Networking support' CONFIG_NET + +bool 'PCI support' CONFIG_PCI +if [ "$CONFIG_PCI" = "y" ]; then + choice ' PCI access mode' \ + "BIOS CONFIG_PCI_GOBIOS \ + Direct CONFIG_PCI_GODIRECT \ + Any CONFIG_PCI_GOANY" Any + if [ "$CONFIG_PCI_GOBIOS" = "y" -o "$CONFIG_PCI_GOANY" = "y" ]; then + define_bool CONFIG_PCI_BIOS y + fi + if [ "$CONFIG_PCI_GODIRECT" = "y" -o "$CONFIG_PCI_GOANY" = "y" ]; then + define_bool CONFIG_PCI_DIRECT y + fi +fi + +source drivers/pci/Config.in + +bool 'Support for hot-pluggable devices' CONFIG_HOTPLUG + +if [ "$CONFIG_HOTPLUG" = "y" ] ; then + source drivers/pcmcia/Config.in + source drivers/hotplug/Config.in +# source drivers/mmc/Config.in +else + define_bool CONFIG_PCMCIA n + define_bool CONFIG_HOTPLUG_PCI n +# define_bool CONFIG_MMC n +fi + +bool 'System V IPC' CONFIG_SYSVIPC +bool 'BSD Process Accounting' CONFIG_BSD_PROCESS_ACCT +bool 'Sysctl support' CONFIG_SYSCTL +if [ "$CONFIG_PROC_FS" = "y" ]; then + choice 'Kernel core (/proc/kcore) format' \ + "ELF CONFIG_KCORE_ELF \ + A.OUT CONFIG_KCORE_AOUT" ELF +fi +tristate 'Kernel support for a.out binaries' CONFIG_BINFMT_AOUT +tristate 'Kernel support for ELF binaries' CONFIG_BINFMT_ELF +tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC + +bool 'Power Management support' CONFIG_PM + +#if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then +# dep_bool ' ACPI support' CONFIG_ACPI $CONFIG_PM +# +# if [ "$CONFIG_ACPI" != "n" ]; then +# source drivers/acpi/Config.in +# fi +#fi + +#bool 'Advanced Power Management BIOS support' CONFIG_APM +#if [ "$CONFIG_APM" != "n" ]; then +# bool ' Ignore USER SUSPEND' CONFIG_APM_IGNORE_USER_SUSPEND +# bool ' Enable PM at boot time' CONFIG_APM_DO_ENABLE +# bool ' Make CPU Idle calls when idle' CONFIG_APM_CPU_IDLE +# bool ' Enable console blanking using APM' CONFIG_APM_DISPLAY_BLANK +# bool ' Ignore multiple suspend/resume cycles' CONFIG_APM_IGNORE_SUSPEND_BOUNCE +# bool ' RTC stores time in GMT' CONFIG_APM_RTC_IS_GMT +# bool ' Allow interrupts during APM BIOS calls' CONFIG_APM_ALLOW_INTS +# bool ' Use real mode APM BIOS call to power off' CONFIG_APM_REAL_MODE_POWER_OFF +#fi + +endmenu + +source drivers/mtd/Config.in + +source drivers/parport/Config.in + +source drivers/pnp/Config.in + +source drivers/block/Config.in + +source drivers/md/Config.in + +if [ "$CONFIG_NET" = "y" ]; then + source net/Config.in +fi + +source drivers/telephony/Config.in + +mainmenu_option next_comment +comment 'ATA/IDE/MFM/RLL support' + +tristate 'ATA/IDE/MFM/RLL support' CONFIG_IDE + +if [ "$CONFIG_IDE" != "n" ]; then + source drivers/ide/Config.in +else + define_bool CONFIG_BLK_DEV_HD n +fi +endmenu + +mainmenu_option next_comment +comment 'SCSI support' + +tristate 'SCSI support' CONFIG_SCSI + +if [ "$CONFIG_SCSI" != "n" ]; then + source drivers/scsi/Config.in +fi +endmenu + +source drivers/message/fusion/Config.in + +source drivers/ieee1394/Config.in + +source drivers/message/i2o/Config.in + +if [ "$CONFIG_NET" = "y" ]; then + mainmenu_option next_comment + comment 'Network device support' + + bool 'Network device support' CONFIG_NETDEVICES + if [ "$CONFIG_NETDEVICES" = "y" ]; then + source drivers/net/Config.in + if [ "$CONFIG_ATM" = "y" ]; then + source drivers/atm/Config.in + fi + fi + endmenu +fi + +source net/ax25/Config.in + +source net/irda/Config.in + +mainmenu_option next_comment +comment 'ISDN subsystem' +if [ "$CONFIG_NET" != "n" ]; then + tristate 'ISDN support' CONFIG_ISDN + if [ "$CONFIG_ISDN" != "n" ]; then + source drivers/isdn/Config.in + fi +fi +endmenu + +mainmenu_option next_comment +comment 'Old CD-ROM drivers (not SCSI, not IDE)' + +bool 'Support non-SCSI/IDE/ATAPI CDROM drives' CONFIG_CD_NO_IDESCSI +if [ "$CONFIG_CD_NO_IDESCSI" != "n" ]; then + source drivers/cdrom/Config.in +fi +endmenu + +# +# input before char - char/joystick depends on it. As does USB. +# +source drivers/input/Config.in +source drivers/char/Config.in + +#source drivers/misc/Config.in + +source drivers/media/Config.in + +source fs/Config.in + +if [ "$CONFIG_VT" = "y" ]; then + mainmenu_option next_comment + comment 'Console drivers' + bool 'VGA text console' CONFIG_VGA_CONSOLE + bool 'Video mode selection support' CONFIG_VIDEO_SELECT + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then + tristate 'MDA text console (dual-headed) (EXPERIMENTAL)' CONFIG_MDA_CONSOLE + source drivers/video/Config.in + fi + endmenu +fi + +mainmenu_option next_comment +comment 'Sound' + +tristate 'Sound card support' CONFIG_SOUND +if [ "$CONFIG_SOUND" != "n" ]; then + source drivers/sound/Config.in +fi +endmenu + +source drivers/usb/Config.in + +if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then + source net/bluetooth/Config.in + +# source drivers/mmc/Config.in +fi + +mainmenu_option next_comment +comment 'Kernel hacking' + +bool 'Kernel debugging' CONFIG_DEBUG_KERNEL +if [ "$CONFIG_DEBUG_KERNEL" != "n" ]; then + bool ' Debug memory allocations' CONFIG_DEBUG_SLAB + bool ' Memory mapped I/O debugging' CONFIG_DEBUG_IOVIRT + bool ' Magic SysRq key' CONFIG_MAGIC_SYSRQ + bool ' Spinlock debugging' CONFIG_DEBUG_SPINLOCK + bool ' Verbose BUG() reporting (adds 70K)' CONFIG_DEBUG_BUGVERBOSE + bool ' Compile the kernel with frame pointers' CONFIG_FRAME_POINTER +fi + +int 'Kernel messages buffer length shift (0 = default)' CONFIG_LOG_BUF_SHIFT 0 + +endmenu + +source crypto/Config.in +source lib/Config.in diff -ruN linux-2.4.26.org/arch/m32r/defconfig linux-2.4.26/arch/m32r/defconfig --- linux-2.4.26.org/arch/m32r/defconfig 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/defconfig 2004-03-22 10:55:18.000000000 +0900 @@ -0,0 +1,674 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_M32R=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# Target processor type and platforms +# +# CONFIG_PLAT_MAPPI is not set +# CONFIG_PLAT_MAPPI2 is not set +# CONFIG_PLAT_M32700UT_Alpha is not set +CONFIG_PLAT_M32700UT=y +# CONFIG_PLAT_USRV is not set +CONFIG_CHIP_M32700=y +# CONFIG_CHIP_XNUX2 is not set +# CONFIG_CHIP_VDEC2 is not set +CONFIG_HAVE_M32R_MMU=y +CONFIG_ISA_M32R2=y +CONFIG_ISA_DSP_LEVEL2=y +CONFIG_ISA_DUAL_ISSUE=y +CONFIG_MEMORY_START=08000000 +CONFIG_MEMORY_SIZE=01000000 +CONFIG_CPU_CLOCK=300000000 +CONFIG_BUS_CLOCK=100000000 +CONFIG_TIMER_DIVIDE=128 +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_USE_INITRD=y +CONFIG_INITRD_START=08300000 +CONFIG_INITRD_SIZE=00400000 +# CONFIG_INITRD_ADDR is not set +# CONFIG_SMP is not set + +# +# Devices for M32R +# +CONFIG_M32R_SERIAL=y +# CONFIG_M32R_USE_DBG_CONSOLE is not set +CONFIG_M32R_PLD_SERIAL=y +CONFIG_M32R_ETHERNET=y +# CONFIG_M32R_NE2000 is not set +CONFIG_M32R_SMC91111=y +CONFIG_MAPPI2_SMC91111=y +CONFIG_M32700UT_SMC91111=y +# CONFIG_M32R_FLASH is not set +CONFIG_M32R_MTD=y +CONFIG_MTD_M32R=y +# CONFIG_MTD_M5 is not set +CONFIG_M32R_CFC=y +CONFIG_MAPPI2_CFC=y +CONFIG_M32700UT_CFC=y +CONFIG_CFC_NUM=1 +CONFIG_M32R_AR=y +CONFIG_M32R_AR_VGA=y +# CONFIG_M32700UT_DS1302 is not set +# CONFIG_USRV_DIPSW is not set +# CONFIG_IDC_AK4524 is not set +# CONFIG_IDC_PARPORT is not set +# CONFIG_IDC_PWRSRC is not set + +# +# General setup +# +CONFIG_NET=y +# CONFIG_PCI is not set +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=y +# CONFIG_TCIC is not set +# CONFIG_I82365 is not set + +# +# PCI Hotplug Support +# +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_REDBOOT_PARTS=y + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_NOSWAP is not set +CONFIG_MTD_CFI_BE_BYTE_SWAP=y +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_CFI_B1 is not set +CONFIG_MTD_CFI_B2=y +# CONFIG_MTD_CFI_B4 is not set +CONFIG_MTD_CFI_I1=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set + +# +# Appletalk devices +# +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# ATA/IDE/MFM/RLL support +# +CONFIG_IDE=m + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD_IDE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_COMMERIAL is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_IDE_CHIPSETS is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_DMA_NONPCI is not set +# CONFIG_BLK_DEV_ATARAID is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION_BOOT is not set +# CONFIG_FUSION_ISENSE is not set +# CONFIG_FUSION_CTL is not set +# CONFIG_FUSION_LAN is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +CONFIG_NET_RADIO=y +# CONFIG_STRIP is not set +# CONFIG_WAVELAN is not set +# CONFIG_ARLAN is not set +# CONFIG_AIRONET4500 is not set +# CONFIG_HERMES is not set + +# +# Wireless Pcmcia cards support +# +# CONFIG_AIRO_CS is not set +CONFIG_NET_WIRELESS=y + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Input core support +# +CONFIG_INPUT=y +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=64 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_SERIO is not set + +# +# Joysticks +# +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_PCMCIA_SERIAL_CS is not set + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=y + +# +# Video For Linux +# +CONFIG_VIDEO_PROC_FS=y + +# +# Video Adapters +# +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_CPIA is not set + +# +# Radio Adapters +# +# CONFIG_RADIO_CADET is not set +# CONFIG_RADIO_RTRACK is not set +# CONFIG_RADIO_RTRACK2 is not set +# CONFIG_RADIO_AZTECH is not set +# CONFIG_RADIO_GEMTEK is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_MAESTRO is not set +# CONFIG_RADIO_SF16FMI is not set +# CONFIG_RADIO_TERRATEC is not set +# CONFIG_RADIO_TRUST is not set +# CONFIG_RADIO_TYPHOON is not set +# CONFIG_RADIO_ZOLTRIX is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +# CONFIG_UMSDOS_FS is not set +CONFIG_VFAT_FS=y +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_CRAMFS=y +CONFIG_TMPFS=y +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +CONFIG_MINIX_FS=y +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_ZISOFS_FS is not set +CONFIG_ZLIB_FS_INFLATE=y + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Console drivers +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VIDEO_SELECT is not set +# CONFIG_MDA_CONSOLE is not set + +# +# Frame-buffer support +# +CONFIG_FB=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FB_EPSON=y +CONFIG_FBCON_EPSON=y +# CONFIG_FB_EPSON_S1D13504 is not set +# CONFIG_FB_EPSON_S1D13505 is not set +# CONFIG_FB_EPSON_S1D13506 is not set +# CONFIG_FB_EPSON_S1D13704 is not set +# CONFIG_FB_EPSON_S1D13705 is not set +# CONFIG_FB_EPSON_S1D13706 is not set +CONFIG_FB_EPSON_S1D13806=y +CONFIG_FBCON_EPSON_S1D13806=y +# CONFIG_FB_EPSON_S1D13A03 is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_FBCON_ADVANCED=y +# CONFIG_FBCON_MFB is not set +# CONFIG_FBCON_CFB2 is not set +# CONFIG_FBCON_CFB4 is not set +# CONFIG_FBCON_CFB8 is not set +CONFIG_FBCON_CFB16=y +# CONFIG_FBCON_CFB24 is not set +# CONFIG_FBCON_CFB32 is not set +# CONFIG_FBCON_AFB is not set +# CONFIG_FBCON_ILBM is not set +# CONFIG_FBCON_IPLAN2P2 is not set +# CONFIG_FBCON_IPLAN2P4 is not set +# CONFIG_FBCON_IPLAN2P8 is not set +# CONFIG_FBCON_MAC is not set +# CONFIG_FBCON_VGA_PLANES is not set +# CONFIG_FBCON_VGA is not set +# CONFIG_FBCON_HGA is not set +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set +CONFIG_FBCON_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_M32R_USB=y +# CONFIG_USB is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Kernel hacking +# +# CONFIG_DEBUG_KERNEL is not set diff -ruN linux-2.4.26.org/arch/m32r/drivers/8390.h linux-2.4.26/arch/m32r/drivers/8390.h --- linux-2.4.26.org/arch/m32r/drivers/8390.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/drivers/8390.h 2003-06-13 22:17:09.000000000 +0900 @@ -0,0 +1 @@ +#include "../../../drivers/net/8390.h" diff -ruN linux-2.4.26.org/arch/m32r/drivers/Config.in linux-2.4.26/arch/m32r/drivers/Config.in --- linux-2.4.26.org/arch/m32r/drivers/Config.in 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/drivers/Config.in 2004-04-20 15:50:13.000000000 +0900 @@ -0,0 +1,62 @@ +# +# Device configuration for M32R platform +# +mainmenu_option next_comment +comment 'Devices for M32R' + +bool 'Character devices' CONFIG_M32R_SERIAL +if [ "$CONFIG_M32R_SERIAL" = "y" ]; then + bool ' Use M32R Dbg_console' CONFIG_M32R_USE_DBG_CONSOLE n + bool ' Use onboard PLD serial' CONFIG_M32R_PLD_SERIAL n +fi + +bool 'Network devices' CONFIG_M32R_ETHERNET +if [ "$CONFIG_M32R_ETHERNET" = "y" ]; then + tristate ' Use onboard NIC(NE2000)' CONFIG_M32R_NE2000 + tristate ' Use onboard NIC(SMC91111)' CONFIG_M32R_SMC91111 +fi +# workaround for +# arch/m32r/kernel/setup_mappi.c +# arch/m32r/kernel/setup_mappi2.c +if [ "$CONFIG_M32R_NE2000" = "y" ]; then + define_bool CONFIG_MAPPI_NE2000 y +fi +if [ "$CONFIG_M32R_SMC91111" = "y" ]; then + define_bool CONFIG_MAPPI2_SMC91111 y + define_bool CONFIG_M32700UT_SMC91111 y +fi + +bool 'Block devices' CONFIG_M32R_FLASH +if [ "$CONFIG_M32R_FLASH" = "y" ]; then + tristate ' Use onboard Flash Memory(M5M29GT320)' CONFIG_M32R_M5 +fi + +bool 'Memory Technology Devices(MTD)' CONFIG_M32R_MTD +if [ "$CONFIG_M32R_MTD" = "y" ]; then + dep_tristate ' Flash device mapped on M32R' CONFIG_MTD_M32R $CONFIG_MTD + dep_tristate ' Support for Renesas flash chips' CONFIG_MTD_M5 $CONFIG_MTD +fi + +dep_bool 'Use onboard PLD CompactFlash (CFC)' CONFIG_M32R_CFC $CONFIG_PCMCIA +if [ "$CONFIG_M32R_CFC" = "y" ]; then + define_bool CONFIG_MAPPI2_CFC y + define_bool CONFIG_M32700UT_CFC y + int ' CF slot number' CONFIG_CFC_NUM 1 +fi + +bool 'AR devices' CONFIG_M32R_AR +if [ "$CONFIG_M32R_AR" = "y" ]; then + tristate ' Use Colour AR module (VGA)' CONFIG_M32R_AR_VGA +fi + +bool 'DS1302 Real Time Clock support' CONFIG_M32700UT_DS1302 + +tristate 'uServer dip switch driver' CONFIG_USRV_DIPSW +tristate 'uServer (IDC-R) AK4524 CODEC chip driver' CONFIG_IDC_AK4524 +tristate 'uServer (IDC-R) parallel port driver' CONFIG_IDC_PARPORT +tristate 'uServer (IDC-R) power source check driver' CONFIG_IDC_PWRSRC + +bool 'Battery Control MCU driver' CONFIG_M32700UT_MCU +dep_tristate 'Touch Screen driver for M32700UT' CONFIG_M32700UT_TS $CONFIG_M32700UT_MCU + +endmenu diff -ruN linux-2.4.26.org/arch/m32r/drivers/Makefile linux-2.4.26/arch/m32r/drivers/Makefile --- linux-2.4.26.org/arch/m32r/drivers/Makefile 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/drivers/Makefile 2004-04-20 15:50:13.000000000 +0900 @@ -0,0 +1,34 @@ +# +# $Id: Makefile,v 1.5 2004/04/20 06:50:13 takeo Exp $ +# +# Makefile for the Linux/M32R kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +O_TARGET := m32r_drivers.o + +export-objs := + +obj-y := + +obj-$(CONFIG_M32R_USE_DBG_CONSOLE) += dbg_console.o +obj-$(CONFIG_M32R_PLD_SERIAL) += m32r-pldsio.o +obj-$(CONFIG_M32R_NE2000) += mappi_ne.o +obj-$(CONFIG_M32R_SMC91111) += smc91111.o +obj-$(CONFIG_M32R_M5) += m5.o +obj-$(CONFIG_M32R_CFC) += m32r_cfc.o +obj-$(CONFIG_MTD_M5) += m5drv.o +obj-$(CONFIG_MTD_M32R) += m32r-flash.o +obj-$(CONFIG_M32R_AR_VGA) += arv.o +obj-$(CONFIG_M32700UT_DS1302) += ds1302.o +obj-$(CONFIG_USRV_DIPSW) += usrv_dipsw.o +obj-$(CONFIG_IDC_AK4524) += idc_ak4524.o +obj-$(CONFIG_IDC_PARPORT) += idc_parport.o +obj-$(CONFIG_IDC_PWRSRC) += idc_pwrsrc.o +obj-$(CONFIG_M32700UT_MCU) += m32700ut_mcu.o +obj-$(CONFIG_M32700UT_TS) += m32700ut_ts.o + +include $(TOPDIR)/Rules.make diff -ruN linux-2.4.26.org/arch/m32r/drivers/arv.c linux-2.4.26/arch/m32r/drivers/arv.c --- linux-2.4.26.org/arch/m32r/drivers/arv.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/drivers/arv.c 2003-09-16 19:18:54.000000000 +0900 @@ -0,0 +1,827 @@ +/* + * Colour AR M64278(VGA) driver for Video4Linux + * + * Copyright (C) 2003 Takeo Takahashi + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Some code is taken from AR driver sample program for M3T-M32700UT. + * + * AR driver sample (M32R SDK): + * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION + * AND RENESAS SOLUTIONS CORPORATION + * All Rights Reserved. + * + * 2003-09-01: Support w3cam by Takeo Takahashi + * + * $Id: arv.c,v 1.1 2003/09/16 10:18:54 takata Exp $ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arv.h" + +#if 0 +#define DEBUG(n, args...) printk(args) +#define CHECK_LOST 1 +#else +#define DEBUG(n, args...) +#define CHECK_LOST 0 +#endif + +/* + * USE_INT is always 0, interrupt mode is not available + * on linux due to lack of speed + */ +#define USE_INT 0 /* Don't modify */ + +#define VERSION "0.01" + +#define ar_inl(addr) inl((unsigned long)(addr)) +#define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr)) + +extern struct cpuinfo_m32r boot_cpu_data; + +/* + * CCD pixel size + * Note that M32700UT does not support CIF mode, but QVGA is + * supported by M32700UT hardware using VGA mode of AR LSI. + * + * Supported: VGA (Normal mode, Interlace mode) + * QVGA (Always Interlace mode of VGA) + * + */ +#define AR_WIDTH_VGA 640 +#define AR_HEIGHT_VGA 480 +#define AR_WIDTH_QVGA 320 +#define AR_HEIGHT_QVGA 240 +#define MIN_AR_WIDTH AR_WIDTH_QVGA +#define MIN_AR_HEIGHT AR_HEIGHT_QVGA +#define MAX_AR_WIDTH AR_WIDTH_VGA +#define MAX_AR_HEIGHT AR_HEIGHT_VGA + +/* bits & bytes per pixel */ +#define AR_BITS_PER_PIXEL 16 +#define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8) + +/* line buffer size */ +#define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL) +#define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL) +#define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA + +/* frame size & type */ +#define AR_FRAME_BYTES_VGA (AR_WIDTH_VGA * AR_HEIGHT_VGA * \ + AR_BYTES_PER_PIXEL) +#define AR_FRAME_BYTES_QVGA (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * \ + AR_BYTES_PER_PIXEL) +#define MAX_AR_FRAME_BYTES (MAX_AR_WIDTH * MAX_AR_HEIGHT * \ + AR_BYTES_PER_PIXEL) + +/* capture size */ +#define AR_SIZE_VGA 0 +#define AR_SIZE_QVGA 1 + +/* capture mode */ +#define AR_MODE_INTERLACE 0 +#define AR_MODE_NORMAL 1 + +struct ar_device { + struct video_device vdev; + unsigned int start_capture; // duaring capture in INT. mode. +#if USE_INT + unsigned char *line_buff; // DMA line buffer +#endif + unsigned char *frame[MAX_AR_HEIGHT]; // frame data + short size; // capture size + short mode; // capture mode + int width, height; + int frame_bytes, line_bytes; + wait_queue_head_t wait; + struct semaphore lock; +}; + +static int video_nr = -1; /* video device number (first free) */ +static unsigned char yuv[MAX_AR_FRAME_BYTES]; + +/* module parameters */ +/* default frequency */ +#define DEFAULT_FREQ 50 // 50 or 75 (MHz) is available as BCLK +static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */ +static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */ +static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */ +MODULE_PARM(freq, "i"); +MODULE_PARM(vga, "i"); +MODULE_PARM(vga_interlace, "i"); + +static int ar_initialize(struct video_device *dev); + +/******************************************************************* + * I2C functions + *******************************************************************/ +void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2, unsigned long data3) +{ + int i; + + /* Slave Address */ + ar_outl(addr, PLDI2CDATA); + + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + /* Start */ + ar_outl(1, PLDI2CCND); + + for(i=0; i<1000; i++); + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + + /* Trasfer data 1 */ + ar_outl(data1, PLDI2CDATA); + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); + + /* Ack wait */ + for(i=0; i<1000; i++); + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + + /* Trasfer data 2 */ + ar_outl(data2, PLDI2CDATA); + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); + + /* Ack wait */ + for(i=0; i<1000; i++); + + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + + if(n==3){ + /* Trasfer data 3 */ + ar_outl(data3, PLDI2CDATA); + while ( ar_inl(ARVCR0) & ARVCR0_VDS ); // wait for VSYNC + while ( !(ar_inl(ARVCR0) & ARVCR0_VDS) ); // wait for VSYNC + ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN); + + /* Ack wait */ + for(i=0; i<10000; i++); + + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK ); + } + + /* Stop */ + for(i=0; i<100; i++); + ar_outl(2, PLDI2CCND); + ar_outl(2, PLDI2CCND); + + while( ar_inl(PLDI2CSTS) & PLDI2CSTS_BB ); +} + + +void init_iic(void) +{ + DEBUG(1, "init_iic:\n"); + + /* + * ICU Setting (iic) + */ + /* I2C Setting */ + ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */ + ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */ + ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */ + + /* I2C CLK */ + /* 50MH-100k */ + if (freq == 75) { + ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */ + } else if (freq == 50) { + ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */ + } else { + ar_outl(244, PLDI2CFREQ); /* default:BCLK = 50MHz */ + } + ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */ +} + +/************************************************************************** + * + * Video4Linux Interface functions + * + **************************************************************************/ +static int ar_open(struct video_device *dev, int flags) +{ + DEBUG(1, "ar_open()\n"); + return 0; +} + +static void ar_close(struct video_device *dev) +{ + DEBUG(1, "ar_close()\n"); + ar_outl(0, ARVCR1); // disable AR interrupt +} + +static __inline__ void wait_for_vertical_sync(int exp_line) +{ +#if CHECK_LOST + int tmout = 10000; /* FIXME */ + int l; + + /* + * check HCOUNT because we can not check vertual sync. + */ + for (; tmout >= 0; tmout--) { + l = ar_inl(ARVHCOUNT); + if (l == exp_line) break; + } + if (tmout < 0) + printk("arv: lost %d -> %d\n", exp_line, l); +#else + while (ar_inl(ARVHCOUNT) != exp_line) ; +#endif +} + +static long ar_read(struct video_device *dev, char *buf, unsigned long count, int noblock) +{ + struct ar_device *ar = (struct ar_device *)dev->priv; + long ret = ar->frame_bytes; /* return read bytes */ + unsigned long arvcr1 = 0; + unsigned long flags; + unsigned char *p; + int h, w; + unsigned char *py, *pu, *pv; +#if ! USE_INT + int l; +#endif + + DEBUG(1, "ar_read()\n"); + + if (ar->size == AR_SIZE_QVGA) arvcr1 |= ARVCR1_QVGA; + if (ar->mode == AR_MODE_NORMAL) arvcr1 |= ARVCR1_NORMAL; + + down(&ar->lock); + +#if USE_INT + save_and_cli(flags); + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0xa1871300, M32700_DMA0CR0); + ar_outl(0x01000000, M32700_DMA0CR1); + + // set AR FIFO address as source(BSEL5の領域を使用) + ar_outl(ARDATA32, M32700_DMA0CSA); // 物理アドレスを設定 + ar_outl(ARDATA32, M32700_DMA0RSA); // 物理アドレスを設定 + ar_outl(ar->line_buff, M32700_DMA0CDA); // destination address + ar_outl(ar->line_buff, M32700_DMA0RDA); // reload address + ar_outl(ar->line_bytes, M32700_DMA0CBCUT); // byte count(bytes) + ar_outl(ar->line_bytes, M32700_DMA0RBCUT); // reload count (bytes) + + /* + * Okey , kicks AR LSI to invoke an interrupt + */ + ar->start_capture = 0; + ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1); + restore_flags(flags); + /* .... AR interrupts .... */ + interruptible_sleep_on(&ar->wait); + if (signal_pending(current)) { + printk("arv: interrupted while get frame data.\n"); + ret = -EINTR; + goto out_up; + } +#else /* ! USE_INT */ + /* polling */ + ar_outl(arvcr1, ARVCR1); + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0x8000, M32700_DMAEDET); + ar_outl(0xa0861300, M32700_DMA0CR0); + ar_outl(0x01000000, M32700_DMA0CR1); + ar_outl(ARDATA32, M32700_DMA0CSA); + ar_outl(ARDATA32, M32700_DMA0RSA); + ar_outl(ar->line_bytes, M32700_DMA0CBCUT); + ar_outl(ar->line_bytes, M32700_DMA0RBCUT); + + save_and_cli(flags); + while (ar_inl(ARVHCOUNT) != 0) ; // wait for 0 + if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { + for (h = 0; h < ar->height; h++) { + wait_for_vertical_sync(h); + if (h < (AR_HEIGHT_VGA/2)) + l = h << 1; + else + l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1); + ar_outl(virt_to_phys(ar->frame[l]), M32700_DMA0CDA); + ar_outl(0x8080, M32700_DMAEN); // enable DMA0 + while (!(ar_inl(M32700_DMAEDET) & 0x8000)) ; + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0x8000, M32700_DMAEDET);// clear status + ar_outl(0xa0861300, M32700_DMA0CR0); + } + } else { + for (h = 0; h < ar->height; h++) { + wait_for_vertical_sync(h); + ar_outl(virt_to_phys(ar->frame[h]), M32700_DMA0CDA); + ar_outl(0x8080, M32700_DMAEN); // enable DMA0 + while (!(ar_inl(M32700_DMAEDET) & 0x8000)) ; + ar_outl(0x80000, M32700_DMAEN); // disable DMA0 + ar_outl(0x8000, M32700_DMAEDET);// clear status + ar_outl(0xa0861300, M32700_DMA0CR0); + } + } + restore_flags(flags); +#endif /* ! USE_INT */ + + /* + * convert YUV422 to YUV422P + * +--------------------+ + * | Y0,Y1,... | + * | ..............Yn | + * +--------------------+ + * | U0,U1,........Un | + * +--------------------+ + * | V0,V1,........Vn | + * +--------------------+ + */ + py = yuv; + pu = py + (ar->frame_bytes / 2); + pv = pu + (ar->frame_bytes / 4); + for (h = 0; h < ar->height; h++) { + p = ar->frame[h]; + for (w = 0; w < ar->line_bytes; w += 4) { + *py++ = *p++; + *pu++ = *p++; + *py++ = *p++; + *pv++ = *p++; + } + } + if (copy_to_user(buf, yuv, ar->frame_bytes)) { + printk("arv: failed while copy_to_user yuv.\n"); + ret = -EFAULT; + goto out_up; + } + DEBUG(1, "ret = %d\n", ret); +out_up: + up(&ar->lock); + return ret; +} + +static long ar_write(struct video_device *v, const char *buf, unsigned long count, int noblock) +{ + DEBUG(1, "ar_write()\n"); + return -EINVAL; +} + +static int ar_ioctl(struct video_device *dev, unsigned int cmd, void *arg) +{ + struct ar_device *ar=(struct ar_device *)dev; + + DEBUG(1, "ar_ioctl()\n"); + switch(cmd) { + case VIDIOCGCAP: + { + struct video_capability b; + DEBUG(1, "VIDIOCGCAP:\n"); + strcpy(b.name, ar->vdev.name); + b.type = VID_TYPE_CAPTURE; + b.channels = 0; + b.audios = 0; + b.maxwidth = MAX_AR_WIDTH; + b.maxheight = MAX_AR_HEIGHT; + b.minwidth = MIN_AR_WIDTH; + b.minheight = MIN_AR_HEIGHT; + if (copy_to_user(arg, &b, sizeof(b))) + return -EFAULT; + return 0; + } + case VIDIOCGCHAN: + DEBUG(1, "VIDIOCGCHAN:\n"); + return 0; + case VIDIOCSCHAN: + DEBUG(1, "VIDIOCSCHAN:\n"); + return 0; + case VIDIOCGTUNER: + DEBUG(1, "VIDIOCGTUNER:\n"); + return 0; + case VIDIOCSTUNER: + DEBUG(1, "VIDIOCSTUNER:\n"); + return 0; + case VIDIOCGPICT: + DEBUG(1, "VIDIOCGPICT:\n"); + return 0; + case VIDIOCSPICT: + DEBUG(1, "VIDIOCSPICT:\n"); + return 0; + case VIDIOCCAPTURE: + DEBUG(1, "VIDIOCCAPTURE:\n"); + return -EINVAL; + case VIDIOCGWIN: + { + struct video_window w; + DEBUG(1, "VIDIOCGWIN:\n"); + memset(&w, 0, sizeof(w)); + w.width = ar->width; + w.height = ar->height; + if (copy_to_user(arg, &w, sizeof(w))) + return -EFAULT; + return 0; + } + case VIDIOCSWIN: + { + struct video_window w; + DEBUG(1, "VIDIOCSWIN:\n"); + if (copy_from_user(&w, arg, sizeof(w))) + return -EFAULT; + down(&ar->lock); + if (w.width != AR_WIDTH_QVGA && + w.height != AR_HEIGHT_QVGA) { + if (w.width != AR_WIDTH_VGA && + w.height != AR_HEIGHT_VGA) { + up(&ar->lock); + return -EINVAL; + } + } + ar->width = w.width; + ar->height = w.height; + if (ar->width == AR_WIDTH_VGA) { + ar->size = AR_SIZE_VGA; + ar->frame_bytes = AR_FRAME_BYTES_VGA; + ar->line_bytes = AR_LINE_BYTES_VGA; + if (vga_interlace) + ar->mode = AR_MODE_INTERLACE; + else + ar->mode = AR_MODE_NORMAL; + } else { + ar->size = AR_SIZE_QVGA; + ar->frame_bytes = AR_FRAME_BYTES_QVGA; + ar->line_bytes = AR_LINE_BYTES_QVGA; + ar->mode = AR_MODE_INTERLACE; + } + up(&ar->lock); + return 0; + } + case VIDIOCGFBUF: + DEBUG(1, "VIDIOCGFBUF:\n"); + return -EINVAL; + case VIDIOCSFBUF: + DEBUG(1, "VIDIOCSFBUF:\n"); + return -EINVAL; + case VIDIOCKEY: + DEBUG(1, "VIDIOCKEY:\n"); + return 0; + case VIDIOCGFREQ: + DEBUG(1, "VIDIOCGFREQ:\n"); + return -EINVAL; + case VIDIOCSFREQ: + DEBUG(1, "VIDIOCSFREQ:\n"); + return -EINVAL; + case VIDIOCGAUDIO: + DEBUG(1, "VIDIOCGAUDIO:\n"); + return -EINVAL; + case VIDIOCSAUDIO: + DEBUG(1, "VIDIOCSAUDIO:\n"); + return -EINVAL; + case VIDIOCSYNC: + DEBUG(1, "VIDIOCSYNC:\n"); + return -EINVAL; + case VIDIOCMCAPTURE: + DEBUG(1, "VIDIOCMCAPTURE:\n"); + return -EINVAL; + case VIDIOCGMBUF: + DEBUG(1, "VIDIOCGMBUF:\n"); + return -EINVAL; + case VIDIOCGUNIT: + DEBUG(1, "VIDIOCGUNIT:\n"); + return -EINVAL; + case VIDIOCGCAPTURE: + DEBUG(1, "VIDIOCGCAPTURE:\n"); + return -EINVAL; + case VIDIOCSCAPTURE: + DEBUG(1, "VIDIOCSCAPTURE:\n"); + return -EINVAL; + case VIDIOCSPLAYMODE: + DEBUG(1, "VIDIOCSPLAYMODE:\n"); + return -EINVAL; + case VIDIOCSWRITEMODE: + DEBUG(1, "VIDIOCSWRITEMODE:\n"); + return -EINVAL; + case VIDIOCGPLAYINFO: + DEBUG(1, "VIDIOCGPLAYINFO:\n"); + return -EINVAL; + case VIDIOCSMICROCODE: + DEBUG(1, "VIDIOCSMICROCODE:\n"); + return -EINVAL; + case VIDIOCGVBIFMT: + DEBUG(1, "VIDIOCGVBIFMT:\n"); + return -EINVAL; + case VIDIOCSVBIFMT: + DEBUG(1, "VIDIOCSVBIFMT:\n"); + return -EINVAL; + default: + DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd); + return -ENOIOCTLCMD; + } + return 0; +} + +#if USE_INT +/* + * Interrupt handler + */ +static void ar_interrupt(int irq, void *dev, struct pt_regs *regs) +{ + struct ar_device *ar = dev; + unsigned int line_count; + unsigned int line_number; + unsigned int arvcr1; + + line_count = ar_inl(ARVHCOUNT); // line number + if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) { + /* operations for interlace mode */ + if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */ + line_number = (line_count << 1); + else /* odd line */ + line_number = + (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1); + } else { + line_number = line_count; + } + + if (line_number == 0) { + /* + * It is an interrupt for line 0. + * we have to start capture. + */ + ar_outl(0x8000, M32700_DMAEN); // disable DMA0 + //ar_outl(ar->line_buff, M32700_DMA0CDA); // needless? + memcpy(ar->frame[0], ar->line_buff, ar->line_bytes); + //ar_outl(0xa1861300, M32700_DMA0CR0); + ar_outl(0x8080, M32700_DMAEN); // enable DMA0 + ar->start_capture = 1; // during capture + return; + } + + if (ar->start_capture == 1 && line_number <= (ar->height - 1)) { + ar_outl(0x8000, M32700_DMAEN); // disable DMA0 + memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes); + + /* + * if captured all line of a frame, disable AR interrupt + * and wake a process up. + */ + if (line_number == (ar->height - 1)) { /* end of line */ + + ar->start_capture = 0; + + /* disable AR interrupt request */ + arvcr1 = ar_inl(ARVCR1); + arvcr1 &= ~ARVCR1_HIEN; // clear int. flag + ar_outl(arvcr1, ARVCR1); // disable + wake_up_interruptible(&ar->wait); + } else { + //ar_outl(ar->line_buff, M32700_DMA0CDA); + //ar_outl(0xa1861300, M32700_DMA0CR0); + ar_outl(0x8080, M32700_DMAEN); // enable DMA + } + } +} +#endif + +/* + * ar_initialize() + * ar_initialize() is called by video_register_device() and + * initializes AR LSI and peripherals. + * + * -1 is returned in all failures. + * 0 is returned in success. + * + */ +static int ar_initialize(struct video_device *dev) +{ + struct ar_device *ar = (struct ar_device *)dev->priv; + unsigned long cr = 0; + int i; + + DEBUG(1, "ar_initialize:\n"); + + /* + * initialize AR LSI + */ + ar_outl(0, ARVCR0); // assert reset of AR LSI + for( i=0; i<0x10; i++); // wait for over 10 cycles + ar_outl(ARVCR0_RST, ARVCR0); // negate reset of AR LSI (enable) + for( i=0; i<0x200; i++); // wait for over 420 cycles + + /* AR uses INT3 of CPU as interrupt pin. */ + ar_outl(ARINTSEL_INT3, ARINTSEL); + + if (ar->size == AR_SIZE_QVGA) cr |= ARVCR1_QVGA; + if (ar->mode == AR_MODE_NORMAL) cr |= ARVCR1_NORMAL; + ar_outl(cr, ARVCR1); + + /* + * Initialize IIC so that CPU can communicate with AR LSI, + * and send boot commands to AR LSI. + */ + init_iic(); + iic(2,0x78,0x11,0x01,0x00); + iic(3,0x78,0x12,0x00,0x06); + iic(3,0x78,0x12,0x12,0x30); + iic(3,0x78,0x12,0x15,0x58); + iic(3,0x78,0x12,0x17,0x30); + iic(3,0x78,0x12,0x1a,0x97); + iic(3,0x78,0x12,0x1b,0xff); + iic(3,0x78,0x12,0x1c,0xff); + iic(3,0x78,0x12,0x26,0x10); + iic(3,0x78,0x12,0x27,0x00); + iic(2,0x78,0x34,0x02,0x00); + iic(2,0x78,0x7a,0x10,0x00); + iic(2,0x78,0x80,0x39,0x00); + iic(2,0x78,0x81,0xe6,0x00); + iic(2,0x78,0x8d,0x00,0x00); + iic(2,0x78,0x8e,0x0c,0x00); + iic(2,0x78,0x8f,0x00,0x00); + iic(2,0x78,0x93,0x01,0x00); + iic(2,0x78,0x94,0xcd,0x00); + iic(2,0x78,0x95,0x00,0x00); + iic(2,0x78,0x96,0xa0,0x00); + iic(2,0x78,0x97,0x00,0x00); + iic(2,0x78,0x98,0x60,0x00); + iic(2,0x78,0x99,0x01,0x00); + iic(2,0x78,0x9a,0x19,0x00); + iic(2,0x78,0x9b,0x02,0x00); + iic(2,0x78,0x9c,0xe8,0x00); + iic(2,0x78,0x9d,0x02,0x00); + iic(2,0x78,0x9e,0x2e,0x00); + iic(2,0x78,0xb8,0x78,0x00); + iic(2,0x78,0xba,0x05,0x00); +// iic(2,0x78,0x83,0x8a,0x00); // 明るさ設定 + iic(2,0x78,0x11,0x00,0x00); // 設定終了 + return 0; +} + +/**************************************************************************** + * + * Video4Linux Module functions + * + ****************************************************************************/ +static struct video_device ar_template = { + owner: THIS_MODULE, + name: "Colour AR VGA", + type: VID_TYPE_CAPTURE, + hardware: 52, + open: ar_open, + close: ar_close, + read: ar_read, + write: ar_write, + ioctl: ar_ioctl, + initialize: ar_initialize, +}; + +#define ALIGN4(x) ((((int)(x)) & 0x3) == 0) +static struct ar_device ardev; + +static int __init ar_init(void) +{ + struct ar_device *ar; + int ret; + int i; + + DEBUG(1, "ar_init:\n"); + ret = -EIO; + printk(KERN_INFO "%s: Colour AR VGA driver %s\n", __FILE__, VERSION); + + ar = &ardev; + memset(ar, 0, sizeof(struct ar_device)); + memcpy(&ar->vdev, &ar_template, sizeof(ar_template)); + +#if USE_INT + /* allocate a DMA buffer for 1 line. */ + ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA); + if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) { + printk("arv: buffer allocation failed for DMA.\n"); + ret = -ENOMEM; + goto out_end; + } +#endif + /* allocate buffers for a frame */ + for (i = 0; i < MAX_AR_HEIGHT; i++) { + ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL); + if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) { + printk("arv: buffer allocation failed for frame.\n"); + ret = -ENOMEM; + goto out_line_buff; + } + } + ar->vdev.priv = ar; + if (vga) { + ar->width = AR_WIDTH_VGA; + ar->height = AR_HEIGHT_VGA; + ar->size = AR_SIZE_VGA; + ar->frame_bytes = AR_FRAME_BYTES_VGA; + ar->line_bytes = AR_LINE_BYTES_VGA; + if (vga_interlace) + ar->mode = AR_MODE_INTERLACE; + else + ar->mode = AR_MODE_NORMAL; + } else { + ar->width = AR_WIDTH_QVGA; + ar->height = AR_HEIGHT_QVGA; + ar->size = AR_SIZE_QVGA; + ar->frame_bytes = AR_FRAME_BYTES_QVGA; + ar->line_bytes = AR_LINE_BYTES_QVGA; + ar->mode = AR_MODE_INTERLACE; + } + init_MUTEX(&ar->lock); + init_waitqueue_head(&ar->wait); + +#if USE_INT + if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)){ + printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3); + ret = -EIO; + goto out_irq; + } +#endif + + /* + * ok, we can initialize h/w according to parameters, + * so register video device as a frame grabber type. + * device is named "video[0-64]". + * video_register_device() initializes h/w using ar_initialize(). + */ + if (video_register_device(&ar->vdev, VFL_TYPE_GRABBER, video_nr)!=0) { + /* return -1, -ENFILE(full) or others */ + printk("arv: register video (Colour AR) failed.\n"); + ret = -ENODEV; + goto out_dev; + } + printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n", + ar->vdev.minor, M32R_IRQ_INT3, freq); + return 0; + +out_dev: +#if USE_INT + free_irq(M32R_IRQ_INT3, ar); +out_irq: +#endif + for (i = 0; i < MAX_AR_HEIGHT; i++) + if (ar->frame[i]) kfree(ar->frame[i]); +out_line_buff: +#if USE_INT + kfree(ar->line_buff); +out_end: +#endif + return ret; +} + +static int __init ar_init_module(void) +{ + freq = (boot_cpu_data.bus_clock / 1000000); + printk("arv: Bus clock %d\n", freq); + if (freq != 50 || freq != 70) + freq = DEFAULT_FREQ; + return ar_init(); +} + +static void __exit ar_cleanup_module(void) +{ + struct ar_device *ar; + int i; + + ar = &ardev; + video_unregister_device(&ar->vdev); +#if USE_INT + free_irq(M32R_IRQ_INT3, ar); +#endif + for (i = 0; i < MAX_AR_HEIGHT; i++) + if (ar->frame[i]) kfree(ar->frame[i]); +#if USE_INT + kfree(ar->line_buff); +#endif +} + +module_init(ar_init_module); +module_exit(ar_cleanup_module); + +MODULE_AUTHOR("Takeo Takahashi "); +MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux"); +MODULE_LICENSE("GPL"); +EXPORT_NO_SYMBOLS; diff -ruN linux-2.4.26.org/arch/m32r/drivers/arv.h linux-2.4.26/arch/m32r/drivers/arv.h --- linux-2.4.26.org/arch/m32r/drivers/arv.h 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/drivers/arv.h 2003-09-16 19:18:54.000000000 +0900 @@ -0,0 +1,384 @@ +/* + * include/asm/m32700.h + * + * Control registers and Special function registers of M32700 + * + * Copyright (c) 2003 Takeo Takahashi + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * $Id: arv.h,v 1.1 2003/09/16 10:18:54 takata Exp $ + * + * 2003-08-26: Bug fixed. M32700_DMA0BCUT => M32700_DMA0CBCUT + * by Takeo Takahashi + * + */ + +#ifndef _M32700_H +#define _M32700_H + +#ifndef M32700_IAMOD +#define M32700_IAMOD 0 /* default IAMOD=0 */ +#endif + +#if M32700_IAMOD +#define M32700_IAMOD_SFR (0x03e00000) +#else +#define M32700_IAMOD_SFR (0x00e00000) +#endif + +#ifndef __ASSEMBLY__ +#define M32700_SFR_BASE (M32700_IAMOD_SFR) +#define __reg8 (volatile unsigned char *) +#define __reg16 (volatile unsigned short *) +#define __reg32 (volatile unsigned int *) +#else +#define M32700_SFR_BASE (M32700_IAMOD_SFR) +#define __reg8 +#define __reg16 +#define __reg32 +#endif /* __ASSEMBLY__ */ + +/************************************************* + * Control Registers accessed directly + *************************************************/ +/* + * Instruction TLB table + */ +#define M32700_ITBL_NUMS 32 +#define M32700_ITBL_BASE (0xfe000000) +#define M32700_DTBL_NUMS 32 +#define M32700_DTBL_BASE (0xfe000800) + +/* + * MMU + */ +#define M32700_MMU_BASE (0xffff0000) +#define M32700_MMU_MATM __reg32(M32700_MMU_BASE + 0x00000000) +#define M32700_MMU_MPSZ __reg32(M32700_MMU_BASE + 0x00000004) +#define M32700_MMU_MASID __reg32(M32700_MMU_BASE + 0x00000008) +#define M32700_MMU_MESTS __reg32(M32700_MMU_BASE + 0x0000000c) +#define M32700_MMU_MDEVA __reg32(M32700_MMU_BASE + 0x00000010) +#define M32700_MMU_MDEVP __reg32(M32700_MMU_BASE + 0x00000014) +#define M32700_MMU_MSVA __reg32(M32700_MMU_BASE + 0x00000020) +#define M32700_MMU_MTOP __reg32(M32700_MMU_BASE + 0x00000024) +#define M32700_MMU_MIDXI __reg32(M32700_MMU_BASE + 0x00000028) +#define M32700_MMU_MIDXD __reg32(M32700_MMU_BASE + 0x0000002c) + +/* + * Cache + */ +#define M32700_CACHE_BASE (0xfffffff0) +#define M32700_CACHE_MCICAR __reg32(M32700_CACHE_BASE + 0x00000000) +#define M32700_CACHE_MCDCAR __reg32(M32700_CACHE_BASE + 0x00000004) +#define M32700_CACHE_MCCR __reg32(M32700_CACHE_BASE + 0x0000000c) + +/* + * EIT + */ +#define M32700_EIT_RI (0x00000000) +#define M32700_EIT_EVB (0x00000000) /* this means offset */ +#define M32700_EIT_SBI __reg32(M32700_EIT_EVB + 0x00000010) +#define M32700_EIT_RIE __reg32(M32700_EIT_EVB + 0x00000020) +#define M32700_EIT_AE __reg32(M32700_EIT_EVB + 0x00000030) +#define M32700_EIT_TRAP0 __reg32(M32700_EIT_EVB + 0x00000040) +#define M32700_EIT_TRAP1 __reg32(M32700_EIT_EVB + 0x00000044) +#define M32700_EIT_TRAP2 __reg32(M32700_EIT_EVB + 0x00000048) +#define M32700_EIT_TRAP3 __reg32(M32700_EIT_EVB + 0x0000004c) +#define M32700_EIT_TRAP4 __reg32(M32700_EIT_EVB + 0x00000050) +#define M32700_EIT_TRAP5 __reg32(M32700_EIT_EVB + 0x00000054) +#define M32700_EIT_TRAP6 __reg32(M32700_EIT_EVB + 0x00000058) +#define M32700_EIT_TRAP7 __reg32(M32700_EIT_EVB + 0x0000005c) +#define M32700_EIT_TRAP8 __reg32(M32700_EIT_EVB + 0x00000060) +#define M32700_EIT_TRAP9 __reg32(M32700_EIT_EVB + 0x00000064) +#define M32700_EIT_TRAP10 __reg32(M32700_EIT_EVB + 0x00000068) +#define M32700_EIT_TRAP11 __reg32(M32700_EIT_EVB + 0x0000006c) +#define M32700_EIT_TRAP12 __reg32(M32700_EIT_EVB + 0x00000070) +#define M32700_EIT_TRAP13 __reg32(M32700_EIT_EVB + 0x00000074) +#define M32700_EIT_TRAP14 __reg32(M32700_EIT_EVB + 0x00000078) +#define M32700_EIT_TRAP15 __reg32(M32700_EIT_EVB + 0x0000007c) +#define M32700_EIT_EI __reg32(M32700_EIT_EVB + 0x00000080) +#define M32700_EIT_PIE __reg32(M32700_EIT_EVB + 0x00000100) +#define M32700_EIT_IACE __reg32(M32700_EIT_EVB + 0x00000110) +#define M32700_EIT_DACE __reg32(M32700_EIT_EVB + 0x00000110) +#define M32700_EIT_ITME __reg32(M32700_EIT_EVB + 0x00000120) +#define M32700_EIT_DTME __reg32(M32700_EIT_EVB + 0x00000120) + +/* + * Multi-Processor + */ +#define M32700_MP_BASE (0xffffffe0) +#define M32700_MP_CPUID __reg32(M32700_MP_BASE + 0x00000000) + +/************************************************* + * Special Function Registers accessed by io/out + *************************************************/ + +/* + * Programable Port + */ +#define M32700_P0IEN __reg8(M32700_SFR_BASE + 0x000f1000) +#define M32700_P1IEN __reg8(M32700_SFR_BASE + 0x000f1001) +#define M32700_P2IEN __reg8(M32700_SFR_BASE + 0x000f1002) +#define M32700_P3IEN __reg8(M32700_SFR_BASE + 0x000f1003) +#define M32700_P4IEN __reg8(M32700_SFR_BASE + 0x000f1004) +#define M32700_P5IEN __reg8(M32700_SFR_BASE + 0x000f1005) +#define M32700_P6IEN __reg8(M32700_SFR_BASE + 0x000f1006) +#define M32700_P7IEN __reg8(M32700_SFR_BASE + 0x000f1007) +#define M32700_P8IEN __reg8(M32700_SFR_BASE + 0x000f1008) + +#define M32700_P0DIR __reg8(M32700_SFR_BASE + 0x000f1010) +#define M32700_P1DIR __reg8(M32700_SFR_BASE + 0x000f1011) +#define M32700_P2DIR __reg8(M32700_SFR_BASE + 0x000f1012) +#define M32700_P3DIR __reg8(M32700_SFR_BASE + 0x000f1013) +#define M32700_P4DIR __reg8(M32700_SFR_BASE + 0x000f1014) +#define M32700_P5DIR __reg8(M32700_SFR_BASE + 0x000f1015) +#define M32700_P6DIR __reg8(M32700_SFR_BASE + 0x000f1016) +#define M32700_P7DIR __reg8(M32700_SFR_BASE + 0x000f1017) +#define M32700_P8DIR __reg8(M32700_SFR_BASE + 0x000f1018) + +#define M32700_P0PDCR __reg16(M32700_SFR_BASE + 0x000f1020) +#define M32700_P1PDCR __reg16(M32700_SFR_BASE + 0x000f1022) +#define M32700_P2PDCR __reg16(M32700_SFR_BASE + 0x000f1024) +#define M32700_P3PDCR __reg16(M32700_SFR_BASE + 0x000f1026) +#define M32700_P4PDCR __reg16(M32700_SFR_BASE + 0x000f1028) +#define M32700_P5PDCR __reg16(M32700_SFR_BASE + 0x000f102a) +#define M32700_P6PDCR __reg16(M32700_SFR_BASE + 0x000f102c) +#define M32700_P7PDCR __reg16(M32700_SFR_BASE + 0x000f102e) +#define M32700_P8PDCR __reg16(M32700_SFR_BASE + 0x000f1030) + +#define M32700_P0OCR __reg16(M32700_SFR_BASE + 0x000f1040) +#define M32700_P1OCR __reg16(M32700_SFR_BASE + 0x000f1042) +#define M32700_P2OCR __reg16(M32700_SFR_BASE + 0x000f1044) +#define M32700_P3OCR __reg16(M32700_SFR_BASE + 0x000f1046) +#define M32700_P4OCR __reg16(M32700_SFR_BASE + 0x000f1048) +#define M32700_P5OCR __reg16(M32700_SFR_BASE + 0x000f104a) +#define M32700_P6OCR __reg16(M32700_SFR_BASE + 0x000f104c) +#define M32700_P7OCR __reg16(M32700_SFR_BASE + 0x000f104e) +#define M32700_P8OCR __reg16(M32700_SFR_BASE + 0x000f1050) + +#define M32700_P0MOD __reg16(M32700_SFR_BASE + 0x000f1060) +#define M32700_P1MOD __reg16(M32700_SFR_BASE + 0x000f1062) +#define M32700_P2MOD __reg16(M32700_SFR_BASE + 0x000f1064) +#define M32700_P3MOD __reg16(M32700_SFR_BASE + 0x000f1066) +#define M32700_P4MOD __reg16(M32700_SFR_BASE + 0x000f1068) +#define M32700_P5MOD __reg16(M32700_SFR_BASE + 0x000f106a) +#define M32700_P6MOD __reg16(M32700_SFR_BASE + 0x000f106c) +#define M32700_P7MOD __reg16(M32700_SFR_BASE + 0x000f106e) +#define M32700_P8MOD __reg16(M32700_SFR_BASE + 0x000f1070) + +#define M32700_P0DATA __reg8(M32700_SFR_BASE + 0x000f1080) +#define M32700_P1DATA __reg8(M32700_SFR_BASE + 0x000f1081) +#define M32700_P2DATA __reg8(M32700_SFR_BASE + 0x000f1082) +#define M32700_P3DATA __reg8(M32700_SFR_BASE + 0x000f1083) +#define M32700_P4DATA __reg8(M32700_SFR_BASE + 0x000f1084) +#define M32700_P5DATA __reg8(M32700_SFR_BASE + 0x000f1085) +#define M32700_P6DATA __reg8(M32700_SFR_BASE + 0x000f1086) +#define M32700_P7DATA __reg8(M32700_SFR_BASE + 0x000f1087) +#define M32700_P8DATA __reg8(M32700_SFR_BASE + 0x000f1088) + +/* + * ICU + */ +#define M32700_ICUISTS __reg32(M32700_SFR_BASE + 0x000ff004) +#define M32700_ICUIREQ0 __reg32(M32700_SFR_BASE + 0x000ff008) +#define M32700_ICUIREQ1 __reg32(M32700_SFR_BASE + 0x000ff00c) + +#define M32700_ICUSBICR __reg32(M32700_SFR_BASE + 0x000ff018) +#define M32700_ICUIMASK __reg32(M32700_SFR_BASE + 0x000ff01c) + +#define M32700_ICUCR1 __reg32(M32700_SFR_BASE + 0x000ff200) +#define M32700_ICUCR2 __reg32(M32700_SFR_BASE + 0x000ff204) +#define M32700_ICUCR3 __reg32(M32700_SFR_BASE + 0x000ff208) +#define M32700_ICUCR4 __reg32(M32700_SFR_BASE + 0x000ff20c) +#define M32700_ICUCR5 __reg32(M32700_SFR_BASE + 0x000ff210) +#define M32700_ICUCR6 __reg32(M32700_SFR_BASE + 0x000ff214) +#define M32700_ICUCR7 __reg32(M32700_SFR_BASE + 0x000ff218) +#define M32700_ICUCR8 __reg32(M32700_SFR_BASE + 0x000ff21c) +#define M32700_ICUCR16 __reg32(M32700_SFR_BASE + 0x000ff23c) +#define M32700_ICUCR17 __reg32(M32700_SFR_BASE + 0x000ff24c) +#define M32700_ICUCR18 __reg32(M32700_SFR_BASE + 0x000ff244) +#define M32700_ICUCR19 __reg32(M32700_SFR_BASE + 0x000ff248) +#define M32700_ICUCR20 __reg32(M32700_SFR_BASE + 0x000ff24c) +#define M32700_ICUCR21 __reg32(M32700_SFR_BASE + 0x000ff250) +#define M32700_ICUCR32 __reg32(M32700_SFR_BASE + 0x000ff27c) +#define M32700_ICUCR33 __reg32(M32700_SFR_BASE + 0x000ff280) +#define M32700_ICUCR48 __reg32(M32700_SFR_BASE + 0x000ff2bc) +#define M32700_ICUCR49 __reg32(M32700_SFR_BASE + 0x000ff2c0) +#define M32700_ICUCR50 __reg32(M32700_SFR_BASE + 0x000ff2c4) +#define M32700_ICUCR51 __reg32(M32700_SFR_BASE + 0x000ff2c8) + +#define M32700_WKUPCR __reg32(M32700_SFR_BASE + 0x000ff2d8) +#define M32700_IPICR0 __reg32(M32700_SFR_BASE + 0x000ff2dc) +#define M32700_IPICR1 __reg32(M32700_SFR_BASE + 0x000ff2e0) +#define M32700_IPICR2 __reg32(M32700_SFR_BASE + 0x000ff2e4) +#define M32700_IPICR3 __reg32(M32700_SFR_BASE + 0x000ff2e8) +#define M32700_IPICR4 __reg32(M32700_SFR_BASE + 0x000ff2ec) +#define M32700_IPICR5 __reg32(M32700_SFR_BASE + 0x000ff2f0) +#define M32700_IPICR6 __reg32(M32700_SFR_BASE + 0x000ff2f4) +#define M32700_IPICR7 __reg32(M32700_SFR_BASE + 0x000ff2f8) + +/* + * Block Select Controller + */ +#define M32700_BSEL0CR0 __reg32(M32700_SFR_BASE + 0x000f5000) +#define M32700_BSEL1CR0 __reg32(M32700_SFR_BASE + 0x000f5100) +#define M32700_BSEL2CR0 __reg32(M32700_SFR_BASE + 0x000f5200) +#define M32700_BSEL3CR0 __reg32(M32700_SFR_BASE + 0x000f5300) +#define M32700_BSEL4CR0 __reg32(M32700_SFR_BASE + 0x000f5400) +#define M32700_BSEL5CR0 __reg32(M32700_SFR_BASE + 0x000f5500) +#define M32700_BSEL6CR0 __reg32(M32700_SFR_BASE + 0x000f5600) +#define M32700_BSEL7CR0 __reg32(M32700_SFR_BASE + 0x000f5700) + +#define M32700_BSEL0CR1 __reg32(M32700_SFR_BASE + 0x000f5004) +#define M32700_BSEL1CR1 __reg32(M32700_SFR_BASE + 0x000f5104) +#define M32700_BSEL2CR1 __reg32(M32700_SFR_BASE + 0x000f5204) +#define M32700_BSEL3CR1 __reg32(M32700_SFR_BASE + 0x000f5304) +#define M32700_BSEL4CR1 __reg32(M32700_SFR_BASE + 0x000f5404) +#define M32700_BSEL5CR1 __reg32(M32700_SFR_BASE + 0x000f5504) +#define M32700_BSEL6CR1 __reg32(M32700_SFR_BASE + 0x000f5604) +#define M32700_BSEL7CR1 __reg32(M32700_SFR_BASE + 0x000f5704) + +/* + * SDRAMC + */ +#define M32700_SDRF0 __reg32(M32700_SFR_BASE + 0x000f6000) +#define M32700_SDRF1 __reg32(M32700_SFR_BASE + 0x000f6004) +#define M32700_SDIR0 __reg32(M32700_SFR_BASE + 0x000f6008) +#define M32700_SDIR1 __reg32(M32700_SFR_BASE + 0x000f600c) + +#define M32700_SD0ADR __reg32(M32700_SFR_BASE + 0x000f6020) +#define M32700_SD0ER __reg32(M32700_SFR_BASE + 0x000f6024) +#define M32700_SD0TR __reg32(M32700_SFR_BASE + 0x000f6028) +#define M32700_SD0MOD __reg32(M32700_SFR_BASE + 0x000f602c) + +#define M32700_SD1ADR __reg32(M32700_SFR_BASE + 0x000f6040) +#define M32700_SD1ER __reg32(M32700_SFR_BASE + 0x000f6044) +#define M32700_SD1TR __reg32(M32700_SFR_BASE + 0x000f6048) +#define M32700_SD1MOD __reg32(M32700_SFR_BASE + 0x000f604c) + +/* + * PCC + */ +#define M32700_PCCR __reg32(M32700_SFR_BASE + 0x000f7000) +#define M32700_PCADR __reg32(M32700_SFR_BASE + 0x000f7004) +#define M32700_PCMOD __reg32(M32700_SFR_BASE + 0x000f7008) +#define M32700_PCIRC __reg32(M32700_SFR_BASE + 0x000f700c) +#define M32700_PCCSIGCR __reg32(M32700_SFR_BASE + 0x000f7010) +#define M32700_PCATCR __reg32(M32700_SFR_BASE + 0x000f7014) + +/* + * DMAC + */ +#define M32700_DMAEN __reg32(M32700_SFR_BASE + 0x000f8000) +#define M32700_DMAISTS __reg32(M32700_SFR_BASE + 0x000f8004) +#define M32700_DMAEDET __reg32(M32700_SFR_BASE + 0x000f8008) +#define M32700_DMAASTS __reg32(M32700_SFR_BASE + 0x000f800c) + +#define M32700_DMA0CR0 __reg32(M32700_SFR_BASE + 0x000f8100) +#define M32700_DMA0CR1 __reg32(M32700_SFR_BASE + 0x000f8104) +#define M32700_DMA0CSA __reg32(M32700_SFR_BASE + 0x000f8108) +#define M32700_DMA0RSA __reg32(M32700_SFR_BASE + 0x000f810c) +#define M32700_DMA0CDA __reg32(M32700_SFR_BASE + 0x000f8110) +#define M32700_DMA0RDA __reg32(M32700_SFR_BASE + 0x000f8114) +#define M32700_DMA0CBCUT __reg32(M32700_SFR_BASE + 0x000f8118) +#define M32700_DMA0RBCUT __reg32(M32700_SFR_BASE + 0x000f811c) + +#define M32700_DMA1CR0 __reg32(M32700_SFR_BASE + 0x000f8200) +#define M32700_DMA1CR1 __reg32(M32700_SFR_BASE + 0x000f8204) +#define M32700_DMA1CSA __reg32(M32700_SFR_BASE + 0x000f8208) +#define M32700_DMA1RSA __reg32(M32700_SFR_BASE + 0x000f820c) +#define M32700_DMA1CDA __reg32(M32700_SFR_BASE + 0x000f8210) +#define M32700_DMA1RDA __reg32(M32700_SFR_BASE + 0x000f8214) +#define M32700_DMA1CBCUT __reg32(M32700_SFR_BASE + 0x000f8218) +#define M32700_DMA1RBCUT __reg32(M32700_SFR_BASE + 0x000f821c) + +/* + * MFT + */ +#define M32700_MFTCR __reg32(M32700_SFR_BASE + 0x000fc000) +#define M32700_MFTRPR __reg32(M32700_SFR_BASE + 0x000fc004) + +#define M32700_MFT0MOD __reg32(M32700_SFR_BASE + 0x000fc100) +#define M32700_MFT0OS __reg32(M32700_SFR_BASE + 0x000fc104) +#define M32700_MFT0CUT __reg32(M32700_SFR_BASE + 0x000fc108) +#define M32700_MFT0RLD __reg32(M32700_SFR_BASE + 0x000fc10c) +#define M32700_MFT0CMPRLD __reg32(M32700_SFR_BASE + 0x000fc110) + +#define M32700_MFT1MOD __reg32(M32700_SFR_BASE + 0x000fc200) +#define M32700_MFT1OS __reg32(M32700_SFR_BASE + 0x000fc204) +#define M32700_MFT1CUT __reg32(M32700_SFR_BASE + 0x000fc208) +#define M32700_MFT1RLD __reg32(M32700_SFR_BASE + 0x000fc20c) +#define M32700_MFT1CMPRLD __reg32(M32700_SFR_BASE + 0x000fc210) + +#define M32700_MFT2MOD __reg32(M32700_SFR_BASE + 0x000fc300) +#define M32700_MFT2OS __reg32(M32700_SFR_BASE + 0x000fc304) +#define M32700_MFT2CUT __reg32(M32700_SFR_BASE + 0x000fc308) +#define M32700_MFT2RLD __reg32(M32700_SFR_BASE + 0x000fc30c) +#define M32700_MFT2CMPRLD __reg32(M32700_SFR_BASE + 0x000fc310) + +#define M32700_MFT3MOD __reg32(M32700_SFR_BASE + 0x000fc400) +#define M32700_MFT3OS __reg32(M32700_SFR_BASE + 0x000fc404) +#define M32700_MFT3CUT __reg32(M32700_SFR_BASE + 0x000fc408) +#define M32700_MFT3RLD __reg32(M32700_SFR_BASE + 0x000fc40c) +#define M32700_MFT3CMPRLD __reg32(M32700_SFR_BASE + 0x000fc410) + +#define M32700_MFT4MOD __reg32(M32700_SFR_BASE + 0x000fc500) +#define M32700_MFT4OS __reg32(M32700_SFR_BASE + 0x000fc504) +#define M32700_MFT4CUT __reg32(M32700_SFR_BASE + 0x000fc508) +#define M32700_MFT4RLD __reg32(M32700_SFR_BASE + 0x000fc50c) +#define M32700_MFT4CMPRLD __reg32(M32700_SFR_BASE + 0x000fc510) + +#define M32700_MFT5MOD __reg32(M32700_SFR_BASE + 0x000fc600) +#define M32700_MFT5OS __reg32(M32700_SFR_BASE + 0x000fc604) +#define M32700_MFT5CUT __reg32(M32700_SFR_BASE + 0x000fc608) +#define M32700_MFT5RLD __reg32(M32700_SFR_BASE + 0x000fc60c) +#define M32700_MFT5CMPRLD __reg32(M32700_SFR_BASE + 0x000fc610) + +/* + * SIO + */ +#define M32700_SIO0CR __reg32(M32700_SFR_BASE + 0x000fd000) +#define M32700_SIO0MOD0 __reg32(M32700_SFR_BASE + 0x000fd004) +#define M32700_SIO0MOD1 __reg32(M32700_SFR_BASE + 0x000fd008) +#define M32700_SIO0STS __reg32(M32700_SFR_BASE + 0x000fd00c) +#define M32700_SIO0TRCR __reg32(M32700_SFR_BASE + 0x000fd010) +#define M32700_SIO0BAUR __reg32(M32700_SFR_BASE + 0x000fd014) +#define M32700_SIO0RBAUR __reg32(M32700_SFR_BASE + 0x000fd018) +#define M32700_SIO0TXB __reg32(M32700_SFR_BASE + 0x000fd01c) +#define M32700_SIO0RXB __reg32(M32700_SFR_BASE + 0x000fd020) + +#define M32700_SIO1CR __reg32(M32700_SFR_BASE + 0x000fd100) +#define M32700_SIO1MOD0 __reg32(M32700_SFR_BASE + 0x000fd104) +#define M32700_SIO1MOD1 __reg32(M32700_SFR_BASE + 0x000fd108) +#define M32700_SIO1STS __reg32(M32700_SFR_BASE + 0x000fd10c) +#define M32700_SIO1TRCR __reg32(M32700_SFR_BASE + 0x000fd110) +#define M32700_SIO1BAUR __reg32(M32700_SFR_BASE + 0x000fd114) +#define M32700_SIO1RBAUR __reg32(M32700_SFR_BASE + 0x000fd118) +#define M32700_SIO1TXB __reg32(M32700_SFR_BASE + 0x000fd11c) +#define M32700_SIO1RXB __reg32(M32700_SFR_BASE + 0x000fd120) + +/* + * WDT + */ +#define M32700_WDTCR __reg32(M32700_SFR_BASE + 0x000f2000) + +/* + * Clock + */ +#define M32700_PLLCR __reg32(M32700_SFR_BASE + 0x000f4004) +#define M32700_MASTERCR __reg32(M32700_SFR_BASE + 0x000f4008) +#define M32700_CPU0DIV __reg32(M32700_SFR_BASE + 0x000f4010) +#define M32700_CPU1DIV __reg32(M32700_SFR_BASE + 0x000f4014) +#define M32700_BIFDIV __reg32(M32700_SFR_BASE + 0x000f4020) +#define M32700_BCLKDIV __reg32(M32700_SFR_BASE + 0x000f4024) +#define M32700_FCLKSEL __reg32(M32700_SFR_BASE + 0x000f4028) +#define M32700_CPU0STOP __reg32(M32700_SFR_BASE + 0x000f4030) +#define M32700_CPU1STOP __reg32(M32700_SFR_BASE + 0x000f4034) +#define M32700_STNBY __reg32(M32700_SFR_BASE + 0x000f404c) +#define M32700_CDIVST __reg32(M32700_SFR_BASE + 0x000f4050) + +#endif /* _M32700_H */ diff -ruN linux-2.4.26.org/arch/m32r/drivers/dbg_console.c linux-2.4.26/arch/m32r/drivers/dbg_console.c --- linux-2.4.26.org/arch/m32r/drivers/dbg_console.c 1970-01-01 09:00:00.000000000 +0900 +++ linux-2.4.26/arch/m32r/drivers/dbg_console.c 2004-01-06 21:43:54.000000000 +0900 @@ -0,0 +1,3609 @@ +/* $Id: dbg_console.c,v 1.4 2004/01/06 12:43:54 takeo Exp $ + * + * Much of the design and some of the code came from serial.c: + * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, + * 1998, 1999 Theodore Ts'o + * + * M32R work: + * Copyright (C) 2000,2001 by Hiro Kondo, Hiro Takata, and Hitoshi Yamamoto. + * + */ + +static char *serial_version = "kondo"; +static char *serial_revdate = "2002-09-11"; +static char *serial_name = "M32R Serial driver"; + +#define LOCAL_VERSTRING "" + +#undef DC_DEBUG + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* serial_state */ +#include /* kmalloc */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_PLAT_USRV) +#undef SERIAL_BH +#define SERIAL_BH MACSERIAL_BH +#endif + +extern struct console console_for_debug; + +static int dc_write(struct tty_struct *tty, int from_user, + const unsigned char *buf, int count); +static int dc_write_room(struct tty_struct *tty); +static int dc_chars_in_buffer(struct tty_struct *tty); + +static void dbg_console_write(struct console *, const char *, unsigned); +static kdev_t dbg_console_device(struct console *c); +void dc_interrupt_single(int, void *, struct pt_regs *); +static void dc_receive_chars(struct async_struct *, int *); + +static void dc_wait_until_sent(struct tty_struct *, int); +static void change_speed(struct async_struct *,struct termios *); +static void autoconfig(struct serial_state *); +static unsigned detect_uart_irq (struct serial_state *); + +static struct tty_driver dc_driver; +static int dc_refcount; + +#define RS_STROBE_TIME (10*HZ) +#define RS_ISR_PASS_LIMIT 256 + +/* number of characters left in xmit buffer before we ask for more */ +#define WAKEUP_CHARS 256 + +static struct async_struct *IRQ_ports[NR_IRQS]; +static int IRQ_timeout[NR_IRQS]; +#ifdef CONFIG_SERIAL_CONSOLE +static struct console cons; +static int lsr_break_flag; +#endif + +#define BAUDRATE 38400 /* Set Baudrate */ +#define BAUDRATE 115200 /* Set Baudrate */ +#define BAUDRATE 19200 /* Set Baudrate */ + +/* + * Here we define the default xmit fifo size used for each type of + * UART + */ +static struct serial_uart_config uart_config[] = { + { "unknown", 1, 0 }, + { "8250", 1, 0 }, + { "16450", 1, 0 }, + { "16550", 1, 0 }, + { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, + { "cirrus", 1, 0 }, /* usurped by cyclades.c */ + { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH }, + { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | + UART_STARTECH }, + { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO}, + { "Startech", 1, 0}, /* usurped by cyclades.c */ + { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO}, + { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | + UART_STARTECH }, + { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | + UART_STARTECH }, + { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }, + { "m32102", 1, 0 }, + { 0, 0} +}; + +#ifdef CONFIG_LINUX_2_2 +static struct serial_state rs_table[] = { + { 0, BAUD9600, 0x3F8, 4, STD_COM_FLAGS }, +}; +#else +static struct serial_state rs_table[RS_TABLE_SIZE] = { +/* UART CLK PORT IRQ FLAGS */ + { 0, BAUDRATE, 0xa0efd000, 48, STD_COM_FLAGS }, + { 0, BAUDRATE, 0xa0efd100, 50, STD_COM_FLAGS }, +#if 0 + SERIAL_PORT_DFNS /* Defined in serial.h */ +#endif +}; +#endif +#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state)) + + +#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) + +static DECLARE_TASK_QUEUE(tq_dc_serial); +static struct tty_struct *dc_table[NR_PORTS]; +static struct termios *dc_termios[NR_PORTS]; +static struct termios *dc_termios_locked[NR_PORTS]; + +#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT) +#define DBG_CNT(s) printk("(%s): [%x] refc=%d, serc=%d, ttyc=%d -> %s\n", \ + kdevname(tty->device), (info->flags), serial_refcount,info->count,tty->count,s +) +#else +#define DBG_CNT(s) +#endif + + +static struct timer_list serial_timer; + +static unsigned char *tmp_buf; +#ifdef DECLARE_MUTEX +static DECLARE_MUTEX(tmp_buf_sem); +#else +static struct semaphore tmp_buf_sem = MUTEX; +#endif + +#if defined(CONFIG_PLAT_MAPPI) || defined(CONFIG_PLAT_MAPPI2) \ + || defined(CONFIG_PLAT_USRV) +static int dbg_console_setup(struct console *console, char *options); +static int sio_putchar(int); + +#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP) +#include +#define _X(x) ((volatile unsigned long *)((x) + __PAGE_OFFSET)) +#define SIO0CR _X(M32R_SIO0_CR_PORTL) +#define SIO0MOD0 _X(M32R_SIO0_MOD0_PORTL) +#define SIO0MOD1 _X(M32R_SIO0_MOD1_PORTL) +#define SIO0STS _X(M32R_SIO0_STS_PORTL) +#define SIO0IMASK _X(M32R_SIO0_TRCR_PORTL) +#define SIO0BAUR _X(M32R_SIO0_BAUR_PORTL) +#define SIO0RBAUR _X(M32R_SIO0_RBAUR_PORTL) +#define SIO0TXB _X(M32R_SIO0_TXB_PORTL) +#define SIO0RXB _X(M32R_SIO0_RXB_PORTL) +#endif + + +#define SIO_IMASK_TEMPIE (1UL<<0) /* b31: enable */ +#define SIO_IMASK_RXCEN (1UL<<2) /* b29: enable */ +#define SIO_IMASK_REIE (1UL<<3) /* b28: enable */ +#define SIO_SIO0STS_TEMP (1UL<<0) /* Transmitter Register Empty */ +#define SIO_SIO0STS_TXCP (1UL<<1) +#define SIO_SIO0STS_RXCP (1UL<<2) +#define SIO_SIO0STS_OERR (1UL<<5) +#define SIO_SIO0STS_PERR (1UL<<6) +#define SIO_SIO0STS_FERR (1UL<<7) +#define SIO_SIO0MOD0_RTSS (1UL<<7) +#define SIO_SIO0MOD0_CTSS (1UL<<6) +#define SIO_NONE (0UL) + +#define UART_TX ((unsigned char *)SIO0TXB - (unsigned char *)SIO0CR) +#define UART_RX ((unsigned char *)SIO0RXB - (unsigned char *)SIO0CR) +#define UART_IER ((unsigned char *)SIO0IMASK - (unsigned char *)SIO0CR) +#define UART_IER_THRI SIO_IMASK_TEMPIE +#define UART_IER_MSI SIO_NONE +#define UART_IER_RLSI SIO_IMASK_REIE +#define UART_IER_RDI SIO_IMASK_RXCEN +#define UART_LSR ((unsigned char *)SIO0STS - (unsigned char *)SIO0CR) +#define UART_LSR_DR SIO_SIO0STS_RXCP +#define UART_LSR_THRE SIO_SIO0STS_TEMP +#define UART_LSR_TEMT SIO_SIO0STS_TXCP +#define UART_LSR_BI SIO_NONE +#define UART_LSR_PE SIO_SIO0STS_PERR +#define UART_LSR_FE SIO_SIO0STS_FERR +#define UART_LSR_OE SIO_SIO0STS_OERR +#define UART_IIR ((unsigned char *)SIO0STS - (unsigned char *)SIO0CR) +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_LCR ((unsigned char *)SIO0CR - (unsigned char *)SIO0CR) +#define UART_LCR_SBC SIO_NONE +#define UART_LCR_PARITY SIO_NONE +#define UART_LCR_EPAR SIO_NONE +#define UART_LCR_SPAR SIO_NONE +#define UART_MCR ((unsigned char *)SIO0MOD0 - (unsigned char *)SIO0CR) +#ifdef CONFIG_CHIP_M32700 +#define UART_MCR_RTS SIO_SIO0MOD0_RTSS +#define UART_MCR_DTR SIO_NONE +#else /* not CONFIG_CHIP_M32700 */ +#define UART_MCR_RTS SIO_SIO0MOD0_RTSS +#define UART_MCR_DTR SIO_SIO0MOD0_CTSS +#endif /* not CONFIG_CHIP_M32700 */ +#define UART_MCR_LOOP SIO_NONE +#define UART_MCR_OUT1 SIO_NONE +#define UART_MCR_OUT2 SIO_NONE +#define UART_MSR ((unsigned char *)SIO0MOD0 - (unsigned char *)SIO0CR) +#define UART_MSR_DCD SIO_NONE +#define UART_MSR_RI SIO_NONE +#define UART_MSR_DSR SIO_NONE +#define UART_MSR_CTS SIO_NONE + +#define UART_BAUR ((unsigned char *)SIO0BAUR - (unsigned char *)SIO0CR) +#define UART_RBAUR ((unsigned char *)SIO0RBAUR - (unsigned char *)SIO0CR) +#define UART_MOD0 ((unsigned char *)SIO0MOD0 - (unsigned char *)SIO0CR) +#define UART_MOD1 ((unsigned char *)SIO0MOD1 - (unsigned char *)SIO0CR) + +static inline unsigned int dc_in(struct async_struct *info,int offset) +{ + return *(volatile unsigned int *)(info->port + offset); +} +static inline void dc_out(struct async_struct *info,int offset,int value) +{ + *(volatile unsigned int *)(info->port + offset) = value; +} + +#define serial_in(info, offset) dc_in(info,(int)offset) +#define serial_out(info, offset, value) dc_out(info,(int)offset, value) +#define serial_inp(info, offset) dc_in(info,(int)offset) +#define serial_outp(info, offset, value) dc_out(info,(int)offset, value) + + +static inline int sio_putchar(int c) +{ + int save_psw; + + if(c){ + __asm__ __volatile__ ( + "mvfc r1,psw\n\t" + "mv %0,r1\n\t" + "and3 r1,r1,#0x0000ffbf\n\t" + "mvtc r1,psw\n" + :"=r" (save_psw):: "r1"); + + if(c < 0x80){ + while((*SIO0STS & SIO_SIO0STS_TEMP) == 0); + *SIO0TXB = c; + } + + __asm__ __volatile__ ( + "mv r1,%0\n\t" + "mvtc r1,psw\n" + ::"r" (save_psw): "r1"); + } + return(c); +} + +#endif /* CONFIG_PLAT_MAPPI */ + +static inline int serial_paranoia_check(struct async_struct *info, + kdev_t device, const char *routine) +{ +#ifdef SERIAL_PARANOIA_CHECK + static const char *badmagic = + "Warning: bad magic number for serial struct (%s) in %s\n"; + static const char *badinfo = + "Warning: null async_struct for (%s) in %s\n"; + + if (!info) { + printk(badinfo, kdevname(device), routine); + return 1; + } + if (info->magic != SERIAL_MAGIC) { + printk(badmagic, kdevname(device), routine); + return 1; + } +#endif + return 0; +} + +/* + * ------------------------------------------------------------ + * dc_stop() and dc_start() + * + * This routines are called before setting or resetting tty->stopped. + * They enable or disable transmitter interrupts, as necessary. + * ------------------------------------------------------------ + */ +static void dc_stop(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->device, "dc_stop")) + return; + + save_flags(flags); cli(); + if (info->IER & UART_IER_THRI) { + info->IER &= ~UART_IER_THRI; + serial_out(info, UART_IER, info->IER); + } +#if 0 /* m32102_sio */ + if (info->state->type == PORT_16C950) { + info->ACR |= UART_ACR_TXDIS; + serial_icr_write(info, UART_ACR, info->ACR); + } +#endif /* m32102_sio */ + restore_flags(flags); + +} + +static void dc_start(struct tty_struct *tty) +{ + struct async_struct *info = (struct async_struct *)tty->driver_data; + unsigned long flags; + + if (serial_paranoia_check(info, tty->device, "dc_start")) + return; + + save_flags(flags); cli(); + if (info->xmit.head != info->xmit.tail + && info->xmit.buf + && !(info->IER & UART_IER_THRI)) { + info->IER |= UART_IER_THRI; + serial_out(info, UART_IER, info->IER); + } +#if 0 /* m32102_sio */ + if (info->state->type == PORT_16C950) { + info->ACR &= ~UART_ACR_TXDIS; + serial_icr_write(info, UART_ACR, info->ACR); + } +#endif /* m32102_sio */ + restore_flags(flags); +} + + +/* + * This routine is used by the interrupt handler to schedule + * processing in the software interrupt portion of the driver. + */ +static inline void dc_sched_event(struct async_struct *info,int event) +{ + info->event |= 1 << event; + queue_task(&info->tqueue, &tq_dc_serial); + mark_bh(SERIAL_BH); +} + +static inline void dc_receive_chars(struct async_struct *info,int *status) +{ + struct tty_struct *tty = info->tty; + unsigned char ch; + struct async_icount *icount; + int max_count = 256; + + icount = &info->state->icount; + do { + if (tty->flip.count >= TTY_FLIPBUF_SIZE) { + tty->flip.tqueue.routine((void *) tty); + if (tty->flip.count >= TTY_FLIPBUF_SIZE) + return; // if TTY_DONT_FLIP is set + } + ch = serial_inp(info, UART_RX); + *tty->flip.char_buf_ptr = ch; + icount->rx++; + +#ifdef SERIAL_DEBUG_INTR + printk("DR%02x:%02x...", ch, *status); +#endif + *tty->flip.flag_buf_ptr = 0; + if (*status & (UART_LSR_BI | UART_LSR_PE | + UART_LSR_FE | UART_LSR_OE)) { + /* + * For statistics only + */ + if (*status & UART_LSR_BI) { + *status &= ~(UART_LSR_FE | UART_LSR_PE); + icount->brk++; + /* + * We do the SysRQ and SAK checking + * here because otherwise the break + * may get masked by ignore_status_mask + * or read_status_mask. + */ +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) + if (info->line == cons.index) { + if (!break_pressed) { + break_pressed = jiffies; + goto ignore_char; + } + break_pressed = 0; + } +#endif + if (info->flags & ASYNC_SAK) + do_SAK(tty); + } else if (*status & UART_LSR_PE) + icount->parity++; + else if (*status & UART_LSR_FE) + icount->frame++; + if (*status & UART_LSR_OE) + icount->overrun++; + + /* + * Mask off conditions which should be ignored. + */ + *status &= info->read_status_mask; + +#ifdef CONFIG_SERIAL_CONSOLE + if (info->line == cons.index) { + /* Recover the break flag from console xmit */ + *status |= lsr_break_flag; + lsr_break_flag = 0; + } +#endif + if (*status & (UART_LSR_BI)) { +#ifdef SERIAL_DEBUG_INTR + printk("handling break...."); +#endif + *tty->flip.flag_buf_ptr = TTY_BREAK; + } else if (*status & UART_LSR_PE) + *tty->flip.flag_buf_ptr = TTY_PARITY; + else if (*status & UART_LSR_FE) + *tty->flip.flag_buf_ptr = TTY_FRAME; + } +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) + if (break_pressed && info->line == cons.index) { + if (ch != 0 && + time_before(jiffies, break_pressed + HZ*5)) { + handle_sysrq(ch, regs, NULL, NULL); + break_pressed = 0; + goto ignore_char; + } + break_pressed = 0; + } +#endif + if ((*status & info->ignore_status_mask) == 0) { + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } +#if 0 /* debug 020115 */ + if ((*status & UART_LSR_OE) && + (tty->flip.count < TTY_FLIPBUF_SIZE)) { + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character + */ + *tty->flip.flag_buf_ptr = TTY_OVERRUN; + tty->flip.count++; + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + } + if ((*status & info->ignore_status_mask) == 0) { + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + tty->flip.count++; + } + if ((*status & UART_LSR_OE) && + (tty->flip.count < TTY_FLIPBUF_SIZE)) { + /* + * Overrun is special, since it's reported + * immediately, and doesn't affect the current + * character + */ + *tty->flip.flag_buf_ptr = TTY_OVERRUN; + tty->flip.count++; + tty->flip.flag_buf_ptr++; + tty->flip.char_buf_ptr++; + } +#endif /* debug 020115 */ +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) + ignore_char: +#endif + *status = serial_inp(info, UART_LSR); + } while ((*status & UART_LSR_DR) && (max_count-- > 0)); +#if (LINUX_VERSION_CODE > 131394) /* 2.1.66 */ + tty_flip_buffer_push(tty); +#else + queue_task_irq_off(&tty->flip.tqueue, &tq_timer); +#endif +} + +static void transmit_chars(struct async_struct *info, int *intr_done) +{ + int count; + + if (info->x_char) { + serial_outp(info, UART_TX, info->x_char); + info->state->icount.tx++; + info->x_char = 0; + if (intr_done) + *intr_done = 0; + while((serial_in(info,UART_LSR) & UART_LSR_TEMT) == 0); + return; + } + if (info->xmit.head == info->xmit.tail + || info->tty->stopped + || info->tty->hw_stopped) { + info->IER &= ~UART_IER_THRI; + serial_out(info, UART_IER, info->IER); + return; + } + count = info->xmit_fifo_size; + count = SERIAL_XMIT_SIZE-1; + do { + serial_out(info, UART_TX, info->xmit.buf[info->xmit.tail]); + info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1); + info->state->icount.tx++; + + if (info->xmit.head == info->xmit.tail) + break; + + while((serial_in(info,UART_LSR) & UART_LSR_THRE) == 0); + } while (--count > 0); + while((serial_in(info,UART_LSR) & UART_LSR_TEMT) == 0); + + if (CIRC_CNT(info->xmit.head, + info->xmit.tail, + SERIAL_XMIT_SIZE) < WAKEUP_CHARS) + dc_sched_event(info, RS_EVENT_WRITE_WAKEUP); + +#ifdef SERIAL_DEBUG_INTR + printk("THRE..."); +#endif + if (intr_done) + *intr_done = 0; + + if (info->xmit.head == info->xmit.tail) { + info->IER &= ~UART_IER_THRI; + serial_out(info, UART_IER, info->IER); + } +} + + +/* +static _INLINE_ void check_modem_status(struct async_struct *info) + +#ifdef CONFIG_SERIAL_SHARE_IRQ +static void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs) +#endif +*/ + +static void sio_reset(struct async_struct *info) +{ +#if defined(CONFIG_PLAT_MAPPI) || defined(CONFIG_PLAT_MAPPI2) \ + || defined(CONFIG_PLAT_USRV) + unsigned int dummy; + /* reset sio */ + dummy=*(volatile char *)(info->port + 0x20); + dummy=*(volatile char *)(info->port + 0x20); + dummy=*(volatile char *)(info->port + 0x0c); + *(volatile char *)(info->port + 0x02) = 3; + *(volatile char *)(info->port + 0x03) = 3; +#endif +} + +static void sio_error(struct async_struct *info,int status) +{ +#if defined(CONFIG_PLAT_MAPPI) || defined(CONFIG_PLAT_MAPPI2) \ + || defined(CONFIG_PLAT_USRV) + unsigned int dummy; + /* reset sio */ + // printk("sio[%d] error[%04x]\n", info->line,status); + dummy=*(volatile char *)(info->port + 0x20); + dummy=*(volatile char *)(info->port + 0x20); + dummy=*(volatile char *)(info->port + 0x0c); + *(volatile char *)(info->port + 0x02) = 3; + *(volatile char *)(info->port + 0x03) = 3; +#endif +} + +static void dc_interrupt_single(int irq, void *dev_id, struct pt_regs * regs) +{ + int status, iir; + // int pass_counter = 0; + struct async_struct * info; + +#ifdef CONFIG_SERIAL_MULTIPORT + int first_multi = 0; + struct rs_multiport_struct *multi; +#endif + +#ifdef SERIAL_DEBUG_INTR + printk("dc_interrupt_single(%d)...", irq); +#endif + + info = IRQ_ports[irq&(~1)]; + if (!info || !info->tty) + return; + +#ifdef CONFIG_SERIAL_MULTIPORT + multi = &rs_multiport[irq]; + if (multi->port_monitor) + first_multi = inb(multi->port_monitor); +#endif + + { + status = serial_inp(info, UART_LSR); +#ifdef SERIAL_DEBUG_INTR + printk("status = %x...", status); +#endif + if (status & UART_LSR_DR){ + dc_receive_chars(info, &status); + } + if (status & 0x0f0f0) { + sio_error(info,status); + }else if(*(volatile unsigned int *)(info->port) !=3){ + sio_error(info,0x666); + } + if (status & UART_LSR_THRE) + transmit_chars(info, 0); +#ifdef SERIAL_DEBUG_INTR + printk("IIR = %x...", serial_in(info, UART_IIR)); +#endif + } + + info->last_active = jiffies; +#ifdef CONFIG_SERIAL_MULTIPORT + if (multi->port_monitor) + printk("rs port monitor (single) irq %d: 0x%x, 0x%x\n", + info->state->irq, first_multi, + inb(multi->port_monitor)); +#endif +#ifdef SERIAL_DEBUG_INTR + printk("end.\n"); +#endif +} +#ifdef CONFIG_SERIAL_MULTIPORT +static void rs_interrupt_multi(int irq, void *dev_id, struct pt_regs * regs) +{} +#endif + +static void do_dc_serial_bh(void) +{ + run_task_queue(&tq_dc_serial); +} + +static void do_softint(void *private_) +{ + struct async_struct *info = (struct async_struct *) private_; + struct tty_struct *tty; + + tty = info->tty; + if (!tty) + return; + + if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) { + if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && + tty->ldisc.write_wakeup) + (tty->ldisc.write_wakeup)(tty); + wake_up_interruptible(&tty->write_wait); +#ifdef SERIAL_HAVE_POLL_WAIT + wake_up_interruptible(&tty->poll_wait); +#endif + } +} + +static void dc_timer(void) +{ + static unsigned long last_strobe = 0; + struct async_struct *info; + unsigned int i; + unsigned long flags; + + if ((jiffies - last_strobe) >= RS_STROBE_TIME) { + for (i=0; i < NR_IRQS; i++) { + info = IRQ_ports[i]; + if (!info) + continue; + save_flags(flags); cli(); + dc_interrupt_single(i, NULL, NULL); + restore_flags(flags); + } + } + last_strobe = jiffies; + +#ifdef CONFIG_LINUX_2_2 +// timer_table[RS_TIMER].expires = jiffies + RS_STROBE_TIME; + timer_table[RS_TIMER].expires = jiffies + 10; + timer_active |= 1 << RS_TIMER; +#else /* not CONFIG_LINUX_2_2 */ +#if 1 + mod_timer(&serial_timer, jiffies + 10); +#else + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME); +#endif +#endif /* not CONFIG_LINUX_2_2 */ + + if (IRQ_ports[0]) { + save_flags(flags); cli(); +#ifdef CONFIG_SERIAL_SHARE_IRQ + dc_interrupt(0, NULL, NULL); +#else + dc_interrupt_single(0, NULL, NULL); +#endif + restore_flags(flags); + + mod_timer(&serial_timer, jiffies + IRQ_timeout[0]); + } +} + +/* + * --------------------------------------------------------------- + * Low level utility subroutines for the serial driver: routines to + * figure out the appropriate timeout for an interrupt chain, routines + * to initialize and startup a serial port, and routines to shutdown a + * serial port. Useful stuff like that. + * --------------------------------------------------------------- + */ + +/* + * This routine figures out the correct timeout for a particular IRQ. + * It uses the smallest timeout of all of the serial ports in a + * particular interrupt chain. Now only used for IRQ 0.... + */ +static void figure_IRQ_timeout(int irq) +{ + struct async_struct *info; + int timeout = 60*HZ; /* 60 seconds === a long time :-) */ + + info = IRQ_ports[irq]; + if (!info) { + IRQ_timeout[irq] = 60*HZ; + return; + } + while (info) { + if (info->timeout < timeout) + timeout = info->timeout; + info = info->next_port; + } + if (!irq) + timeout = timeout / 2; + IRQ_timeout[irq] = timeout ? timeout : 1; +} + +#ifdef CONFIG_SERIAL_RSA +/* Attempts to turn on the RSA FIFO. Returns zero on failure */ +static int enable_rsa(struct async_struct *info) {} + +/* Attempts to turn off the RSA FIFO. Returns zero on failure */ +static int disable_rsa(struct async_struct *info) { } +#endif /* CONFIG_SERIAL_RSA */ + +static int startup(struct async_struct * info) +{ + unsigned long flags; + int retval=0; + void (*handler)(int, void *, struct pt_regs *); + struct serial_state *state= info->state; + unsigned long page; +#ifdef CONFIG_SERIAL_MANY_PORTS + unsigned short ICP; +#endif + + page = get_zeroed_page(GFP_KERNEL); + if (!page) + return -ENOMEM; + + save_flags(flags); cli(); + + if (info->flags & ASYNC_INITIALIZED) { + free_page(page); + goto errout; + } +#if 0 /* 020113 fix*/ + if (!CONFIGURED_SERIAL_PORT(state) || !state->type) { + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + free_page(page); + goto errout; + } +#endif + if (info->xmit.buf) + free_page(page); + else + info->xmit.buf = (unsigned char *) page; + +#ifdef SERIAL_DEBUG_OPEN + printk("starting up ttyD%d (irq %d)...", info->line, state->irq); +#endif + + /* + * Clear the FIFO buffers and disable them + * (they will be reenabled in change_speed()) + */ + + /* + * Clear the interrupt registers. + */ +#if 1 /* for m32r @020114 */ + sio_reset(info); +#else + (void) serial_inp(info, UART_LSR); + (void) serial_inp(info, UART_RX); + (void) serial_inp(info, UART_IIR); + (void) serial_inp(info, UART_MSR); +#endif + +#if 0 /* 020114 */ + /* + * At this point there's no way the LSR could still be 0xFF; + * if it is, then bail out, because there's likely no UART + * here. + */ + /* m32102 note: don't set ASYNC_BUGGY_UART at info->flags */ + if (!(info->flags & ASYNC_BUGGY_UART) && + (serial_inp(info, UART_LSR) == 0xff)) { + printk("ttyS%d: LSR safety check engaged!\n", state->line); + if (capable(CAP_SYS_ADMIN)) { + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + } else + retval = -ENODEV; + goto errout; + } +#endif /* 020114 */ + + /* + * Allocate the IRQ if necessary + */ + if (state->irq && (!IRQ_ports[state->irq] || + !IRQ_ports[state->irq]->next_port)) { + if (IRQ_ports[state->irq]) { +#ifdef CONFIG_SERIAL_SHARE_IRQ + free_irq(state->irq, &IRQ_ports[state->irq]); +#if 1 /* 020116 */ + free_irq(state->irq+1, &IRQ_ports[state->irq]); +#endif +#ifdef CONFIG_SERIAL_MULTIPORT + if (rs_multiport[state->irq].port1) + handler = rs_interrupt_multi; + else +#endif + handler = dc_interrupt; +#else + retval = -EBUSY; + goto errout; +#endif /* CONFIG_SERIAL_SHARE_IRQ */ + } else + handler = dc_interrupt_single; + +#if 1 /* 020116 */ + retval = request_irq(state->irq, handler, SA_SHIRQ, + "serial_rx", &IRQ_ports[state->irq]); + retval = request_irq(state->irq+1, handler, SA_SHIRQ, + "serial_tx", &IRQ_ports[state->irq]); +#else + retval = request_irq(state->irq, handler, SA_SHIRQ, + "serial_rx", &IRQ_ports[state->irq]); +#endif + if (retval) { + if (capable(CAP_SYS_ADMIN)) { + if (info->tty) + set_bit(TTY_IO_ERROR, + &info->tty->flags); + retval = 0; + } + goto errout; + } + } + + /* + * Insert serial port into IRQ chain. + */ + info->prev_port = 0; + info->next_port = IRQ_ports[state->irq]; + if (info->next_port) + info->next_port->prev_port = info; + IRQ_ports[state->irq] = info; + figure_IRQ_timeout(state->irq); + + /* + * Now, initialize the UART + */ +#if 1 /* for m32r @020113 */ + sio_reset(info); +#else + serial_outp(info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ +#endif /* for m32r @020113 */ + + info->MCR = 0; + if (info->tty->termios->c_cflag & CBAUD) + info->MCR = UART_MCR_DTR | UART_MCR_RTS; +#ifdef CONFIG_SERIAL_MANY_PORTS + if (info->flags & ASYNC_FOURPORT) { + if (state->irq == 0) + info->MCR |= UART_MCR_OUT1; + } else +#endif + { + if (state->irq != 0) + info->MCR |= UART_MCR_OUT2; + } + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */ + serial_outp(info, UART_MCR, info->MCR); + + /* + * Finally, enable interrupts + */ + info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; + serial_outp(info, UART_IER, info->IER); /* enable interrupts */ + +#ifdef CONFIG_SERIAL_MANY_PORTS + if (info->flags & ASYNC_FOURPORT) { + /* Enable interrupts on the AST Fourport board */ + ICP = (info->port & 0xFE0) | 0x01F; + outb_p(0x80, ICP); + (void) inb_p(ICP); + } +#endif + + /* + * And clear the interrupt registers again for luck. + */ + (void)serial_inp(info, UART_LSR); + (void)serial_inp(info, UART_RX); + (void)serial_inp(info, UART_IIR); + (void)serial_inp(info, UART_MSR); + + if (info->tty) + clear_bit(TTY_IO_ERROR, &info->tty->flags); + info->xmit.head = info->xmit.tail = 0; + + /* + * Set up serial timers... + */ +#ifdef CONFIG_LINUX_2_2 + timer_table[RS_TIMER].expires = jiffies + 2*HZ/100; + timer_active |= 1 << RS_TIMER; +#else + mod_timer(&serial_timer, jiffies + 2*HZ/100); +#endif + + /* + * Set up the tty->alt_speed kludge + */ +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */ + if (info->tty) { + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) + info->tty->alt_speed = 57600; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) + info->tty->alt_speed = 115200; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) + info->tty->alt_speed = 230400; + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) + info->tty->alt_speed = 460800; + } +#endif + + /* + * and set the speed of the serial port + */ + change_speed(info, 0); + + info->flags |= ASYNC_INITIALIZED; + restore_flags(flags); + return 0; + +errout: + restore_flags(flags); + return retval; +} + +/* + * This routine will shutdown a serial port; interrupts are disabled, and + * DTR is dropped if the hangup on close termio flag is on. + */ +static void shutdown(struct async_struct * info) +{ + unsigned long flags; + struct serial_state *state; + int retval; + + if (!(info->flags & ASYNC_INITIALIZED)) + return; + + state = info->state; + +#ifdef SERIAL_DEBUG_OPEN + printk("Shutting down serial port %d (irq %d)....", info->line, + state->irq); +#endif + + save_flags(flags); cli(); /* Disable interrupts */ + + /* + * clear delta_msr_wait queue to avoid mem leaks: we may free the irq + * here so the queue might never be waken up + */ + wake_up_interruptible(&info->delta_msr_wait); + + /* + * First unlink the serial port from the IRQ chain... + */ + if (info->next_port) + info->next_port->prev_port = info->prev_port; + if (info->prev_port) + info->prev_port->next_port = info->next_port; + else + IRQ_ports[state->irq] = info->next_port; + figure_IRQ_timeout(state->irq); + + /* + * Free the IRQ, if necessary + */ + if (state->irq && (!IRQ_ports[state->irq] || + !IRQ_ports[state->irq]->next_port)) { + if (IRQ_ports[state->irq]) { +#if 1 /* 020116 */ + free_irq(state->irq+1, &IRQ_ports[state->irq]); + retval = request_irq(state->irq+1, dc_interrupt_single, + SA_SHIRQ, "serial_xx", + &IRQ_ports[state->irq]); +#endif /* 020116 */ + free_irq(state->irq, &IRQ_ports[state->irq]); + retval = request_irq(state->irq, dc_interrupt_single, + SA_SHIRQ, "serial", + &IRQ_ports[state->irq]); + + if (retval) + printk("serial shutdown: request_irq: error %d" + " Couldn't reacquire IRQ.\n", retval); + } else{ + free_irq(state->irq, &IRQ_ports[state->irq]); +#if 1 /* 020116 */ + free_irq(state->irq+1, &IRQ_ports[state->irq]); +#endif /* 020116 */ + } + } + if (info->xmit.buf) { + unsigned long pg = (unsigned long) info->xmit.buf; + info->xmit.buf = 0; + free_page(pg); + } + + info->IER = 0; + serial_outp(info, UART_IER, 0x00); /* disable all intrs */ +#ifdef CONFIG_SERIAL_MANY_PORTS + if (info->flags & ASYNC_FOURPORT) { + /* reset interrupts on the AST Fourport board */ + (void) inb((info->port & 0xFE0) | 0x01F); + info->MCR |= UART_MCR_OUT1; + } else +#endif +#if 0 /* 020113 */ + info->MCR &= ~UART_MCR_OUT2; + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */ + + /* disable break condition */ + serial_out(info, UART_LCR, serial_inp(info, UART_LCR) & ~UART_LCR_SBC); +#endif /* 020113 */ + + if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS); + serial_outp(info, UART_MCR, info->MCR); + +#if 0 /* 020113 */ + /* disable FIFO's */ + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO | + UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT)); + serial_outp(info, UART_FCR, 0); +#endif /* 020113 */ + +#ifdef CONFIG_SERIAL_RSA + /* + * Reset the RSA board back to 115kbps compat mode. + */ + if ((state->type == PORT_RSA) && + (state->baud_base == SERIAL_RSA_BAUD_BASE && + disable_rsa(info))) + state->baud_base = SERIAL_RSA_BAUD_BASE_LO; +#endif + + + (void)serial_in(info, UART_RX); /* read data port to reset things */ + + if (info->tty) + set_bit(TTY_IO_ERROR, &info->tty->flags); + +#if 0 /* 020113 */ + if (uart_config[info->state->type].flags & UART_STARTECH) { + /* Arrange to enter sleep mode */ + serial_outp(info, UART_LCR, 0xBF); + serial_outp(info, UART_EFR, UART_EFR_ECB); + serial_outp(info, UART_LCR, 0); + serial_outp(info, UART_IER, UART_IERX_SLEEP); + serial_outp(info, UART_LCR, 0xBF); + serial_outp(info, UART_EFR, 0); + serial_outp(info, UART_LCR, 0); + } + if (info->state->type == PORT_16750) { + /* Arrange to enter sleep mode */ + serial_outp(info, UART_IER, UART_IERX_SLEEP); + } +#endif /* 020113 */ + sio_reset(info); + + info->flags &= ~ASYNC_INITIALIZED; + restore_flags(flags); +} + +static void change_speed(struct async_struct *info,struct termios *old_termios) +{ + int quot = 0, baud_base, baud; + unsigned cflag, cval = 0; + int bits; + unsigned long flags; + unsigned mod0, mod1 , adj; + + if (!info->tty || !info->tty->termios) + return; + cflag = info->tty->termios->c_cflag; + if (!CONFIGURED_SERIAL_PORT(info)) + return; + + /* byte size and parity */ + switch (cflag & CSIZE) { + case CS5: mod1 = 0x05; bits = 7; break; + case CS6: mod1 = 0x06; bits = 8; break; + case CS7: mod1 = 0x07; bits = 9; break; + case CS8: mod1 = 0x08; bits = 10; break; + /* Never happens, but GCC is too dumb to figure it out */ + default: mod1 = 0x05; bits = 7; break; + } + mod1 <<= 8; + mod0 = 0; + if (cflag & CSTOPB) { + mod0 |= 0x03; + bits++; + } + if (cflag & PARENB) { + mod0 |= 0x10; + bits++; + } + if (!(cflag & PARODD)) { + mod0 |= 0x4; + } +#if defined(CONFIG_CHIP_M32700) + if (cflag & CRTSCTS) { + mod0 |= 0